MAX13046E Datasheet, PDF (12/15 Pages) Maxim Integrated Products – Single- and Dual-Bidirectional Low-Level Translator

Single- and Dual-Bidirectional
Low-Level Translator
R_C
1MΩ
R_D
1500Ω
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
HIGH-
VOLTAGE
DC
SOURCE
Cs
100pF
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
R_C
50MΩ TO 100MΩ
R_D
330Ω
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
HIGH-
VOLTAGE
DC
SOURCE
Cs
150pF
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
Figure 2a. Human Body ESD Test Model
Figure 3a. IEC 61000-4-2 ESD Test Model
I_P 100%
90%
AMPERES
36.8%
10%
0
0 _tRL
Ir
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
TIME
t_DL
CURRENT WAVEFORM
Figure 2b. Human Body Current Waveform
I
100%
90%
10%
tr = 0.7ns TO 1ns
30ns
t
60ns
Figure 3b. IEC 61000-4-2 ESD Generator Current Waveform
typical application involves interfacing a low-voltage
microprocessor to an external memory, such as the
DS2502. The maximum data rate depends on the
1-Wire device. For the DS2502, the maximum data rate
is 16.3kbps. A 5kΩ pullup resistor is recommended
when interfacing with the DS2502.
Push-Pull vs. Open-Drain Driving
The MAX13046E/MAX13047E can be driven in a push-
pull or open-drain configurations. For open-drain con-
figuration, internal 10kΩ resistors pull up I/O V_L and I/O
V_CC to their respective power supplies. See the Timing
Characteristics table for maximum data rates when
using open-drain drivers.
PCB Layout
The MAX13046E/MAX13047E require good PCB layout
for proper operation and optimal rise/fall time perfor-
mance. Ensure proper high-frequency PCB layout even
when operating at low data rates.
Driving High-Capacitive Load
Capacitive loading on the I/O lines impacts the rise time
(and fall time) of the MAX13046E/MAX13047E when dri-
ving the signal lines. The actual rise time is a function of
the load capacitance, parasitic capacitance, the supply
voltage, and the drive impedance of the MAX13046E/
MAX13047E.
Operating the MAX13046E/MAX13047E at a low data rate
does NOT increase capacitive load driving capability.
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