MAX11102_11 Datasheet, PDF (12/30 Pages) Maxim Integrated Products – 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs 2.2V to 3.6V Supply Voltage

2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11111) (continued)
(VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 48MHz, 50% duty cycle, 3Msps, CDOUT = 10pF, TA = -40NC to +125NC,
unless otherwise noted. Typical values are at TA = +25NC.)
PARAMETER
DIGITAL INPUTS (SCLK, CS)
Digital Input High Voltage
Digital Input Low Voltage
Digital Input Hysteresis
Digital Input Leakage Current
Digital Input Capacitance
DIGITAL OUTPUT (DOUT)
Output High Voltage
Output Low Voltage
High-Impedance Leakage
Current
High-Impedance Output
Capacitance
POWER SUPPLY
SYMBOL
CONDITIONS
VIH
VIL
VHYST
IIL
CIN
Inputs at GND or VDD
VOH
VOL
IOL
COUT
ISOURCE = 200µA (Note 2)
ISINK = 200µA (Note 2)
MIN TYP MAX UNITS
0.75 x
VOVDD
V
0.25 x
VOVDD
V
0.15 x
VOVDD
V
0.001 Q1
FA
2
pF
0.85 x
VOVDD
V
0.15 x
VOVDD
V
Q1.0
FA
4
pF
Positive Supply Voltage
VDD
Digital I/O Supply Voltage
VOVDD
Positive Supply Current
IVDD
(Full-Power Mode)
IOVDD
Positive Supply Current
(Full-Power Mode), No Clock
IVDD
Power-Down Current
IPD
Line Rejection
TIMING CHARACTERISTICS (Note 1)
VAIN_ = VGND
VAIN_ = VGND
Leakage only
VDD = +2.2V to +3.6V, VREF = 2.2V
2.2
3.6
V
1.5
VDD
V
3.3
mA
0.33
1.98
mA
1.3
10
FA
0.17
LSB/V
Quiet Time
CS Pulse Width
CS Fall to SCLK Setup
CS Falling Until DOUT High-
Impedance Disabled
Data Access Time After SCLK
Falling Edge (Figure 2)
SCLK Pulse Width Low
SCLK Pulse Width High
Data Hold Time From SCLK
Falling Edge
SCLK Falling Until DOUT High-
Impedance
Power-Up Time
tQ
t1
t2
t3
(Note 2)
t4
VOVDD = 2.2V - 3.6V
VOVDD = 1.5V - 2.2V
t5
Percentage of clock period
t6
Percentage of clock period
t7
Figure 3
t8
Figure 4 (Note 2)
Conversion cycle
4
ns
10
ns
5
ns
1
ns
15
ns
16.5
40
60
%
40
60
%
5
ns
2.5
14
ns
1
Cycle
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