MAX11102_11 Datasheet, PDF (10/30 Pages) Maxim Integrated Products – 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs 2.2V to 3.6V Supply Voltage

2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11110/MAX11117) (continued)
(VDD = 2.2V to 3.6V. MAX11110: fSCLK = 32MHz, 50% duty cycle, 2Msps. MAX11117: fSCLK = 48MHz, 50% duty cycle, 3Msps.
CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.)
PARAMETER
DIGITAL OUTPUT (DOUT)
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Output-High Voltage
VOH
ISOURCE = 200µA
0.85 x
VDD
V
Output-Low Voltage
VOL
ISINK = 200µA
0.15 x
VDD
V
High-Impedance Leakage
Current
IOL
Q1.0
FA
High-Impedance Output
Capacitance
COUT
4
pF
POWER SUPPLY
Positive Supply Voltage
Positive Supply Current
(Full-Power Mode)
VDD
IVDD
Positive Supply Current
(Full-Power Mode), No Clock
IVDD
Power-Down Current
IPD
Line Rejection
TIMING CHARACTERISTICS (Note 1)
Quiet Time
tQ
CS Pulse Width
t1
CS Fall to SCLK Setup
t2
CS Falling Until DOUT High-
Impedance Disabled
t3
MAX11117, VAIN = VGND
MAX11110, VAIN = VGND
MAX11117
MAX11110
Leakage only
VDD = +2.2V to +3.6V
(Note 2)
2.2
3.6
V
3.55
mA
2.6
1.98
mA
1.48
1.3
10
FA
0.17
LSB/V
4
ns
10
ns
5
ns
1
ns
Data Access Time After SCLK
Falling Edge
t4
Figure 2, VDD = +2.2V to +3.6V
15
ns
SCLK Pulse Width Low
SCLK Pulse Width High
Data Hold Time From SCLK
Falling Edge
t5
Percentage of clock period
t6
Percentage of clock period
t7
Figure 3
40
60
%
40
60
%
5
ns
SCLK Falling Until DOUT High-
Impedance
t8
Figure 4 (Note 2)
2.5
14
ns
Power-Up Time
Conversion cycle
1
Cycle
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