MAX16041 Datasheet, PDF (11/15 Pages) Maxim Integrated Products – Dual-/Triple-/Quad-Voltage, Capacitor-Adjustable, Sequencing/Supervisory Circuits

Dual-/Triple-/Quad-Voltage, Capacitor-
Adjustable, Sequencing/Supervisory Circuits
Adjustable Reset Timeout Period
(CRESET)
All of these parts offer an internally fixed reset timeout
(140ms min) by connecting CRESET to V_CC. The reset
timeout can also be adjusted by connecting a capaci-
tor from CRESET to GND. When the voltage at CRESET
reaches 0.5V, RESET goes high. When RESET goes
high, CRESET is immediately held low.
Calculate the reset timeout period as follows:
t_RP
=
V_{TH−RESET}
I_{CH−RESET}
× C_CRESET
+ 30 × 10^−6
where V_TH-RESET is 0.5V, I_CH-RESET is 0.5µA, t_RP is in
seconds, and C_CRESET is in Farads. To ensure timing
accuracy and proper operation, minimize leakage at
C_CRESET.
Adjustable Delay (CDLY_)
When V_IN rises above V_TH with EN_ high, the internal
250nA current source begins charging an external
capacitor connected from CDLY_ to GND. When the
voltage at CDLY_ reaches 1V, OUT_ goes high. When
OUT_ goes high, CDLY_ is immediately held low.
Adjust the delay (t_DELAY) from when V_IN rises above
V_TH (with EN_ high) to OUT_ going high according to
the equation:
t_DELAY
=
V_TH−CDLY
I_CH−CDLY
× C_CDLY
+ 35 × 10^−6
where V_TH-CDLY is 1V, I_CH-CDLY is 0.25µA, C_CDLY is in
Farads, and t_DELAY is in seconds. To ensure timing
accuracy and proper operation, minimize leakage
at CDLY.
Manual-Reset Input (MR)
Many µP-based products require manual-reset capabil-
ity, allowing the operator, a test technician, or external
logic circuitry to initiate a reset. A logic-low on MR
asserts RESET low. RESET remains asserted while MR
is low and during the reset timeout period (140ms fixed
or capacitor adjustable) after MR returns high. The MR
input has a 500nA internal pullup, so it can be left
unconnected, if not used. MR can be driven with TTL or
CMOS logic levels, or with open-drain/collector outputs.
Connect a normally open momentary switch from MR to
GND to create a manual-reset function. External
debounce circuitry is not required. If MR is driven from
long cables or if the device is used in a noisy environ-
ment, connect a 0.1µF capacitor from MR to GND to
provide additional noise immunity.
Pullup Resistor Values
The exact value of the pullup resistors for the open-
drain outputs is not critical, but some consideration
should be made to ensure the proper logic levels
when the device is sinking current. For example, if
V_CC = 2.25V and the pullup voltage is 28V, keep the
sink current less than 0.5mA as shown in the Electrical
Characteristics. As a result, the pullup resistor should
be greater than 56kΩ. For a 12V pullup, the resistor
should be larger than 24kΩ. Note that the ability to sink
current is dependent on the V_CC supply voltage.
Power-Supply Bypassing
The device operates with a V_CC supply voltage from
2.2V to 28V. When V_CC falls below the UVLO threshold,
all the outputs go low and stay low until V_CC falls below
1.2V. For noisy systems or fast rising transients on V_CC,
connect a 0.1µF ceramic capacitor from V_CC to GND
as close to the device as possible to provide better
noise and transient immunity.
Ensuring Valid Reset Output
with V_CC Down to 0V
When V_CC falls below 1.2V, the ability for the output to
sink current decreases. To ensure a valid output as
V_CC falls to 0V, connect a 100kΩ resistor from RESET
to GND.
Typical Application Circuits
Figures 4 and 5 show typical applications for the
MAX16041/MAX16042/MAX16043. In high-power appli-
cations, using an n-channel device reduces the loss
across the MOSFETs as it offers a lower drain-to-source
on-resistance. However, an n-channel MOSFET
requires a sufficient V_GS voltage to fully enhance it for a
low R_{DS_ON}. The application in Figure 4 shows the
MAX16042 configured in a multiple-output sequencing
application. Figure 5 shows the MAX16043 in a power-
supply sequencing application using n-channel
MOSFETs.
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