MAX1428 Datasheet, PDF (11/18 Pages) Maxim Integrated Products – 15-Bit, 80Msps ADC with -78.4dBFS Noise Floor for IF Applications

15-Bit, 80Msps ADC with -78.4dBFS
Noise Floor for IF Applications
• t_SETUP: Time from data guaranteed valid until the ris-
ing edge of DAV
• t_HOLD: Time from the rising edge of DAV until data is
no longer valid
• t_CLKP: Time from the 50% point of the rising edge to
the 50% point of the falling edge of the clock signal
• t_CLKN: Time from the 50% point of the falling edge to
the 50% point of the rising edge of the clock signal
The MAX1428 samples the input signal on the rising
edge of the input clock. Output data is valid on the ris-
ing edge of the DAV signal, with a data latency of three
clock cycles. Note that the clock duty cycle must be
50% ±5% for proper operation.
Digital Outputs (D0–D14, DAV, DOR)
The logic-high level of the CMOS-compatible digital
outputs (D0–D14, DAV, and DOR) can be set in the
2.3V to 3.5V range. This is accomplished by setting the
voltage at the DV_CC and DRV_CC pins to the desired
logic-high level. Note that the DV_CC and DRV_CC volt-
ages must be the same value.
For best performance, the capacitive loading on the digital
outputs of the MAX1428 should be kept as low as possible
(<10pF). Large capacitive loads result in large charging
currents during data transitions, which may feed back into
the analog section of the ADC and create distortion terms.
The loading capacitance is kept low by keeping the output
traces short and by driving a single CMOS buffer or latch
input (as opposed to multiple CMOS inputs).
Inserting small series resistors (220Ω or less) between
the MAX1428 outputs and the digital load, placed as
closely as possible to the output pins, is helpful in con-
trolling the size of the charging currents during data
transitions and can improve dynamic performance.
Keep the trace length from the resistor to the load as
short as possible to minimize trace capacitance.
The output data is in two’s complement format, as illus-
trated in Table 1.
Data is valid at the rising edge of DAV (Figure 4), and
DAV can be used as a clock signal to latch the output
data. The DAV output provides twice the drive strength
of the data outputs, and may therefore be used to drive
multiple data latches.
The DOR output is used to identify an overrange condi-
tion. If the input signal exceeds the positive or negative
full-scale range for the MAX1428, then DOR is asserted
high. The timing for DOR is identical to the timing for
the data outputs, and DOR therefore provides an over-
range indication on a sample-by-sample basis.
Table 1. MAX1428 Digital Output Coding
INP
ANALOG VOLTAGE LEVEL
INN
ANALOG VOLTAGE LEVEL
V_REF + 0.64V
V_REF - 0.64V
V_REF
V_REF
V_REF - 0.64V
V_REF + 0.64V
D14–D0
TWO’S COMPLEMENT CODE
011111111111111
(positive full scale)
000000000000000
(midscale + δ)
111111111111111
(midscale - δ)
100000000000000
(negative full scale)
______________________________________________________________________________________ 11