MAX1428 Datasheet, PDF (10/18 Pages) Maxim Integrated Products – 15-Bit, 80Msps ADC with -78.4dBFS Noise Floor for IF Applications

15-Bit, 80Msps ADC with -78.4dBFS
Noise Floor for IF Applications
On-Chip Reference Circuit
The MAX1428 incorporates an on-chip 2.5V, low-drift
bandgap reference. This reference potential establish-
es the full-scale range for the converter, which is nomi-
nally 2.56V_P-P differential. The internal reference
potential is not accessible to the user, so the full-scale
range for the MAX1428 cannot be externally adjusted.
Figure 3 shows how the reference is used to generate
the common-mode bias potential for the analog inputs.
The common-mode input bias is set to two diode poten-
tials above the bandgap reference potential, and so
varies over temperature.
500Ω
1mA
500Ω
2.5V
INP/INN
COMMON-MODE
REFERENCE
1kΩ
2mA
Figure 3. Simplified Reference Architecture
Clock Inputs (CLKP, CLKN)
The differential clock buffer for the MAX1428 has been
designed to accept an AC-coupled clock waveform. Like
the signal inputs, the clock inputs are self-biasing. In this
case, the common-mode bias potential is 2.4V and each
input is connected to the reference potential through a
1kΩ resistor. Consequently, the differential input resis-
tance associated with the clock inputs is 2kΩ. While dif-
ferential clock signals as low as 0.5V_P-P may be used to
drive the clock inputs, best dynamic performance is
achieved with clock input voltage levels of 2V_P-P to 3V_P-P.
Jitter on the clock signal translates directly to jitter (noise)
on the sampled signal. Therefore, the clock source
should be a low-jitter (low phase noise) source. See the
Applications Information section for additional details on
driving the clock inputs.
System Timing Requirements
Figure 4 depicts the timing relationships for the signal
input, clock input, data output, and DAV output. The
variables shown in the figure correspond to the various
timing specifications in the Electrical Characteristics
table. These include:
• t_DAT: Delay from the rising edge of the clock until the
50% point of the output data transition
• t_DAV: Delay from the falling edge of the clock until the
50% point of the DAV rising edge
• t_DNV: Time from the rising edge of the clock until data
is no longer valid
• t_DGV: Time from the rising edge of the clock until data
is guaranteed to be valid
INP
INN
CLKN
CLKP
N
t_DAT
t_AD
N+1
t_DNV
D0–D14
DOR
N-3
N-2
t_DAV
DAV
t_CLKP
N+2
t_DGV
t_CLKN
N+3
N-1
N
t_S
t_H
Figure 4. System and Output Timing Diagram
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