MAX13325_12 Datasheet, PDF (11/21 Pages) Maxim Integrated Products – Dual Automotive, Audio Line Drivers with I2C Control and Diagnostic

MAX13325/MAX13326
Dual Automotive, Audio Line Drivers
with I²C Control and Diagnostic
Table 4. General Fault Register Format
General Faults
FUNCTION
ADDRESS
CODE (HEX)
D7
D6
REGISTER DATA
POR STATE
D5
D4
D3
D2
D1
D0
(HEX)
General Fault
Register
0x02
x
TWARN TSHDN DUMP x
x
x
x
0x00
TWARN: The TWARN bit is set to ‘1’ when the temperature warning threshold is reached.
TSHDN: The TSHDN is set to ‘1’ when the temperature shutdown threshold is reached.
DUMP: The DUMP bit is set to ‘1’ when the VDD voltage exceeds the overvoltage threshold.
Set the appropriate mask bit in the GMASK register to detect the general faults. See Table 8.
Table 5. Left-Channel Fault Register Format
ADDRESS
FUNCTION
CODE
(HEX)
D7
REGISTER DATA
D6
D5
D4
D3
Left-Channel Faults
POR STATE
D2
D1 D0
(HEX)
Left-Channel
Fault Register
0x03
SVDDL SGNDL LIMITL
x OFFSETL OPENL
x
x
0x00
SVDDL: The SVDDL bit is set to ‘1’ when a short to VDD is detected on the left channel.
SGNDL: The SGNDL bit is set to ‘1’ when a short to GND is detected on the left channel.
LIMITL: The LIMITL bit is set to ‘1’ when the current-limit threshold is tripped for left output.
OFFSETL: The OFFSETL bit is set to ‘1’ when excessive offset is detected on the left-channel output.
OPENL: The OPENL bit is set to ‘1’ when an open load is detected on the left channel.
Set the appropriate mask bit in the LMASK register to detect the faults on the left channel. See Table 9.
When any bit of the LFAULT register is high, the FLAG output is low.
Table 6. Right-Channel Fault Register Format
Right-Channel Faults
ADDRESS
FUNCTION
CODE
(HEX)
D7
REGISTER DATA
D6
D5
D4
D3
POR STATE
D2
D1 D0
(HEX)
Right-Channel
Fault Register
0x04
SVDDR SGNDR LIMITR x
OFFSETR OPENR x
x
0x00
SVDDR: The SVDDR bit is set to ‘1’ when a short to VDD is detected on the right channel.
SGNDR: The SGNDR bit is set to ‘1’ when a short to GND is detected on the right channel.
LIMITR: The LIMITR bit is set to ‘1’ when the current-limit threshold is tripped for right output.
OFFSETR: The OFFSETR bit is set to ‘1’ when excessive offset is detected on the right-channel output.
OPENR: The OPENR bit is set to ‘1’ when an open load is detected on the right channel.
Set the appropriate mask bit in the RMASK register to detect the faults on the right channel. See Table 10.
When any bit of the RFAULT register is high, the FLAG output is pulled low.
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