MAX11047 Datasheet, PDF (11/18 Pages) Maxim Integrated Products – 4-/6-/8-Channel, 16-Bit, Simultaneous-Sampling ADCs

4-/6-/8-Channel, 16-Bit,
Simultaneous-Sampling ADCs
R_S
=
V_{FAULT _ MAX}
20mA
− 7V
where V_{FAULT_MAX} is the maximum voltage that the
source produces during a fault condition.
Figures 2 and 3 illustrate the clamp circuit voltage-cur-
rent characteristics for a source impedance R_S =
1280Ω. While the input voltage is within the range of
-300mV to +(V_AVDD + 300mV), no current flows in the
input clamps. Once the input voltage goes beyond this
voltage range, the clamps turn on and limit the voltage
at the input pin.
INPUT
PIN
SIGNAL VOLTAGE
AVDD
R_S
CH0
CLAMP
S/H
SOURCE
CH7
CLAMP
S/H
Applications Information
Digital Interface
The bidirectional, parallel, digital interface, DB0–DB3,
sets the 4-bit configuration register. This interface
configures the following control signals: chip select
(CS), read (RD), write (WR), end of conversion (EOC),
and convert start (CONVST). Figures 6 and 7 and the
Timing Characteristics in the Electrical Characteristics
table show the operation of the interface. DB0–DB3,
together with the output-only DB4–DB15, also output
the 16-bit conversion result. All bits are high imped-
ance when RD = 1 or CS = 1.
16-BIT ADC
16-BIT ADC
DVDD
DB15
DB4
DB3
DB0
AGNDs
AGND
MAX11047
MAX11048
MAX11049
REFIO
BANDGAP
REFERENCE
INT REF
REF
BUF
EXT REF
CONFIGURATION
REGISTERS
INTERFACE
AND
CONTROL
WR
RD
CS
CONVST
SHDN
EOC
RDC
DGND
Figure 1. Required Setup for Clamp Circuit
25
20
R_S = 1170I
V_AVDD = 5.0V
15
10 ^{AT CH_ INPUT}
5
0 _{AT SOURCE}
-5
-10
-15
-20
-25
-30 -20 -10 0 10 20 30 40
SIGNAL VOLTAGE AT SOURCE AND CH_ INPUT (V)
25
20
R_S = 1170I
V_AVDD = 5.0V
15
10
AT CH_ INPUT
5 ^{AT SOURCE}
0
-5
-10
-15
-20
-25
-4 -2
0
2
4
6
8
SIGNAL VOLTAGE AT SOURCE AND CH_ INPUT (V)
Figure 2. Input Clamp Characteristics
Figure 3. Input Clamp Characteristics (Zoom In)
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