DS1338 Datasheet, PDF (11/16 Pages) Maxim Integrated Products – I2C RTC with 56-Byte NV RAM

DS1338 I²C RTC with 56-Byte NV RAM
CONTROL REGISTER (07H)
The control register controls the operation of the SQW/OUT pin and provides oscillator status.
Bit #
Name
POR
BIT 7
OUT
1
BIT 6
0
0
BIT 5
OSF
1
BIT 4
SQWE
1
BIT 3
0
0
BIT 2
0
0
BIT 1
RS1
1
BIT 0
RS0
1
Bit 7: Output Control (OUT). Controls the output level of the SQW/OUT pin when the square-wave output is
disabled. If SQWE = 0, the logic level on the SQW/OUT pin is 1 if OUT = 1; it is 0 if OUT = 0.
Bit 5: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator has stopped or was stopped for
some time period and can be used to judge the validity of the clock and calendar data. This bit is edge triggered,
and is set to logic 1 when the internal circuitry senses the oscillator has transitioned from a normal run state to a
STOP condition. The following are examples of conditions that may cause the OSF bit to be set:
1) The first time power is applied.
2) The voltage present on V_CC and V_BAT are insufficient to support oscillation.
3) The CH bit is set to 1, disabling the oscillator.
4) External influences on the crystal (i.e., noise, leakage, etc.).
This bit remains at logic 1 until written to logic 0. This bit can only be written to logic 0. Attempting to write OSF to
logic 1 leaves the value unchanged.
Bit 4: Square-Wave Enable (SQWE). When set to logic 1, this bit enables the oscillator output to operate with
either V_CC or V_BAT applied. The frequency of the square-wave output depends upon the value of the RS0 and RS1
bits.
Bits 1 and 0: Rate Select (RS1 and RS0). These bits control the frequency of the square-wave output when the
square-wave output has been enabled. The table below lists the square-wave frequencies that can be selected
with the RS bits.
Square-Wave Output
OUT RS1 RS0
X
0
0
X
0
1
X
1
0
X
1
1
0
X
X
1
X
X
SQW OUTPUT
1Hz
4.096kHz
8.192kHz
32.768kHz
0
1
SQWE
1
1
1
1
0
0
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