MAX15012_07 Datasheet, PDF (10/18 Pages) Maxim Integrated Products – 175V/2A, High-Speed, Half-Bridge MOSFET Drivers

175V/2A, High-Speed,
Half-Bridge MOSFET Drivers
Minimum Input Pulse Width
The MAX15012/MAX15013 use a single-shot level-shifter
architecture to achieve low propagation delay. Typical
level shifter architecture causes a minimum (high or low)
pulse width (t_Dmin) at the output that may be higher than
the logic-input pulse width. For the MAX15012/
MAX15013 devices, the DH minimum high pulse-width
(t_Dmin-DH-H) is lower than the DL minimum low pulse
width (t_Dmin-DL-L) to avoid any shoot-through in the
absence of external BBM delay during the narrow pulse
at low duty cycle. See Figure 2.
V_DD
PWMIN
INH
INL
At high duty cycle (close to 100%), the DH minimum low
pulse width (t_Dmin-DH-L) must be higher than the DL min-
imum low pulse width (t_Dmin-DL-L) to avoid the overlap
and shoot-through. See Figure 3. In case of the
MAX15012/MAX15013, there is a possibility of about
40ns overlap if an external BBM delay is not provided. It
is recommended to add external delay in the INH path
so that the minimum low pulse width seen at INH is
always longer than t_PW-min. See the Electrical
Characteristics table for the typical values of t_PW-min.
V_IN
DH
N
HS
V_OUT
DL
N
MAX15012B/
MAX15012D/
MAX15013B/
MAX15013D
PWMIN
DH
t_DMIN-DH-H
IN-BUILT
DEAD TIME
DL
t_DMIN-DL-L
Figure 2. Minimum Pulse-Width Behavior for Narrow Duty-Cycle Input (On-Time < t_PW-min)
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