MAX1077 Datasheet, PDF (10/18 Pages) Maxim Integrated Products – 1.5Msps, Single-Supply, Low-Power, True-Differential, 10-Bit ADCs with Internal Reference

1.5Msps, Single-Supply, Low-Power, True-
Differential, 10-Bit ADCs with Internal Reference
CNVST
SCLK
t_SETUP
12
34
POWER-MODE SELECTION WINDOW
8
t_ACQUIRE
CONTINUOUS-CONVERSION
14
16 ^{SELECTION WINDOW}
HIGH IMPEDANCE
DOUT
Figure 5. Interface-Timing Sequence
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0
CNVST
ONE 8-BIT TRANSFER
CNVST MUST GO HIGH AFTER THE 3RD BUT BEFORE THE 14TH SCLK RISING EDGE
SCLK
1ST SCLK RISING EDGE
DOUT GOES HIGH IMPEDANCE ONCE CNVST GOES HIGH
DOUT
0
0
0 D9 D8 D7 D6 D5
MODE
REF
NORMAL
PPD
ENABLED (2.048V)
Figure 6. SPI Interface—Partial Power-Down Mode
CNVST
SCLK
DOUT
FIRST 8-BIT TRANSFER
EXECUTE PARTIAL POWER-DOWN TWICE
SECOND 8-BIT TRANSFER
1ST SCLK RISING EDGE
1ST SCLK RISING EDGE
0
0
0 D9 D8 D7 D6 D5
DOUT ENTERS TRI-STATE ONCE CNVST GOES HIGH
0
0
0
0
0
0
0
0
MODE
NORMAL
PPD
RECOVERY
FPD
REF
Figure 7. SPI Interface—Full Power-Down Mode
ENABLED (2.048V)
DISABLED
partial power-down mode. Then repeat the same
sequence to enter full power-down mode (see Figure
7). Drive CNVST low, and allow at least 14 SCLK cycles
to elapse before driving CNVST high to exit full power-
down mode. While in full power-down mode, the refer-
ence is disabled to minimize power consumption. Be
sure to allow at least 2ms recovery time after exiting full
power-down mode for the reference to settle. In
partial/full power-down mode, maintain a logic low or a
logic high on SCLK to minimize power consumption.
Transfer Function
Figure 8 shows the unipolar transfer function for the
MAX1077. Figure 9 shows the bipolar transfer function for
the MAX1079. The MAX1077 output is straight binary,
while the MAX1079 output is two’s complement.
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