88F6180_1 Datasheet, PDF (82/112 Pages) –

88F6180
Hardware Specifications
8.6.7
Two-Wire Serial Interface (TWSI) AC Timing
8.6.7.1
TWSI AC Timing Table
Table 47: TWSI Master AC Timing Table
De s cr iption
SCK clock frequency
SCK minimum low level w idth
SCK minimum high level w idth
SDA input setup time relative to SCK rising edge
SDA input hold time relative to SCK falling edge
SDA and SCK rise time
SDA and SCK fall time
SDA output delay relative to SCK falling edge
Sym bol
f CK
tLOW
tHIGH
tSU
tHD
tr
tf
tOV
Min Max
See note 1
0.47
-
0.40
-
250.0
-
0.0
-
-
1000.0
-
300.0
0.0
0.4
Units
kHz
tCK
tCK
ns
ns
ns
ns
tCK
Note s
1
2
2
-
-
2, 3
2, 3
2
Note s :
General comment: All values referred to VIH(min) and VIL(max) levels, unless otherw ise specified.
General comment: tCK = 1/fCK.
1. See "Reference Clocks" table for more details.
2. For all signals, the load is CL = 100 pF, and RL value can be 500 ohm to 8 kilohm.
3. Rise time measured f rom VIL(max) to VIH(min), f all time measured f rom VIH(min) to VIL(max).
Table 48: TWSI Slave AC Timing Table
De s cr iption
SCK minimum low level w idth
SCK minimum high level w idth
SDA input setup time relative to SCK rising edge
SDA input hold time relative to SCK falling edge
SDA and SCK rise time
SDA and SCK fall time
SDA output delay relative to SCK falling edge
Sym bol
tLOW
tHIGH
tSU
tHD
tr
tf
tOV
100 kHz
Min Max
4.7
-
4.0
-
250.0
-
0.0
-
-
1000.0
-
300.0
0.0
4.0
Units
us
us
ns
ns
ns
ns
us
Note s
1
1
-
-
1, 2
1, 2
1
Note s :
General comment: All values referred to VIH(min) and VIL(max) levels, unless otherw ise specified.
1. For all signals, the load is CL = 100 pF, and RL value can be 500 ohm to 8 kilohm.
2. Rise time measured f rom VIL(max) to VIH(min), f all time measured f rom VIH(min) to VIL(max).
Doc. No. MV-S104988-U0 Rev. E
Page 82
Document Classification: Proprietary Information
Copyright © 2008 Marvell
December 2, 2008, Preliminary