88F6180_1 Datasheet, PDF (16/112 Pages) –

88F6180
Hardware Specifications
1.1
Pin Logic
Figure 1: 88F6180 Pin Logic Diagram
VDD
VDDO
VDD_GE
VDD_M
VSS
CPU_PLL_AVDD
CORE_PLL_AVDD
XTAL_AVDD
XTAL_AVSS
PEX_AVDD
USB_AVDD
RTC_AVDD
SSCG_AVDD
SSCG_AVSS
VHV
Power
JT_CLK
JT_TDI
JT_TDO
JT_TMS_CPU
JT_TMS_CORE
JT_RSTn
PEX_CLK_P
PEX_CLK_N
PEX_TX_P
PEX_TX_N
PEX_RX_P
PEX_RX_N
PEX_ISET
USB_DP
USB_DM
NF_CLE
NF_ALE
NF_CEn
NF_REn
NF_WEn
JTAG
PCI Express
USB
NAND
Flash
Misc.
Gigabit Ethernet
SDRAM
MPP
RTC
REF_CLK_XIN
XOUT
SYSRSTn
TP
ISET
MRn
GE_TXCLKOUT
GE_TXD[3:0]
GE_TXCTL
GE_RXD[3:0]
GE_RXCTL
GE_RXCLK
GE_MDC
GE_MDIO
M_CLKOUT
M_CLKOUTn
M_CKE
M_RASn
M_CASn
M_WEn
M_A[13:0]
M_BA[2:0]
M_CSn[1:0]
M_DQ[15:0]
M_DQS[1:0]
M_DQSn[1:0]
M_DM[1:0]
M_ODT
M_STARTBURST
M_STARTBURST_IN
M_PCAL
M_NCAL
MPP[19:0]
MPP[44:35]
RTC_XIN
RTC_XOUT
NOTE: The GE_TXCLKOUT pin is an input only when used as the MII/MMII Transmit Clock.
The MPP interface consists of pin MPP[19:0] and MPP[44:35].
The pins MPP[34:20] do not exist.
For details about MPP configuration options see Section 4.1, Multi-Purpose Pins Functional
Summary, on page 41.
Doc. No. MV-S104988-U0 Rev. E
Page 16
Document Classification: Proprietary Information
Copyright © 2008 Marvell
December 2, 2008, Preliminary