TLF50241EL_15 Datasheet, PDF (9/30 Pages) Marl International Limited – 2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current

TLF50241EL
5
Buck Regulator
5.1
Description
Buck Regulator
The TLF50241EL is a monolithic current mode step down converter with adjustable switching frequency f_OSC. It is
capable to operate either in Pulse Width Modulation (PWM) or in Pulse Frequency Modulation (PFM) Mode.
5.1.1 Regulator Loop
Power stage:
The supply voltage is connected to pin VS. Between pin VS and pin SWO there is an internal shunt resistor and
the internal PMOS power stage. The PMOS is driven by the driver stage.
Regulator Block:
The device is on as soon as an input voltage higher than input voltage startup threshold V_S,on is applied to pin VS.
The feedback signal V_FB is connected to pin FB. Between pin FB and pin GND is an internal resistor divider. An
error amplifier and a comparator are connected to this resistor divider: the error amplifier EA-gmV, which is
controlling the output voltage in PWM mode, and the PFM comparator, which will switch the TLF50241EL into PFM
mode and trigger the pulses. The error amplifier EA-gmV is connected to the PWM comparator. The regulation
loop operates in current mode: the output current of EA-gmV is subtracted from the sum of the current loop CS-
gmI and the slope compensation I_SLOPE. The result is evaluated by PWM Comp (a current comparator). The output
of PWM Comp defines duty cycle (pulse-width-modulated signal) in PWM mode.
The Slope Compensation added to the signal from the error amplifier EA-gmV to the PWM Comparator ensures
that no sub harmonics will occur on the input current.
The PWM comparator output and the PFM comparator output are connected to the PWM /PFM logic.
An external resistor at pin FREQ is required to set the switching frequency (for details please refer to chapter 8
Module Oscillator). The TLF50241EL may also be synchronized to an external frequency. In this case an external
clock signal should be connected to pin SYNC. The frequency setting resistor at pin FREQ is still necessary, it has
to be selected according to the desired synchronization frequency (for details please refer to chapter 8 Module
Oscillator).
The TLF50241EL can only be synchronized to an external frequency source in PWM mode, this function does not
work in PFM mode.
The clock manager is clocking the PWM/PFM logic. The PWM/PFM logic is triggering the driver to apply pulses to
the internal PMOS power stage.
Safety Features:
The shunt resistor in line with the internal PMOS power stage (between pin VS and the power stage) is connected
to a current sense amplifier CS-gml. It detects the voltage above the shunt resistor. The amplifier creates a signal
which shuts the pulse down in case that the shunt voltage exceeds the reference limit. The current limitation acts
as a cycle-by-cycle limitation. Cycle-by-cycle limitation means, that every pulse is switched off as soon as the
current through the PMOS exceeds the buck peak over current limit I_BUOC. The next pulse starts and will also be
switched off as soon as the current limit is exceeded again. This results in a lowered output voltage whilst the
output current is limited to a certain value.
Data Sheet
9
Rev. 1.0, 2013-06-19