TLF50241EL_15 Datasheet, PDF (19/30 Pages) Marl International Limited – 2.2 MHz Step-Down Regulator 500 mA, 5 V, low quiescent current

TLF50241EL
6
Reset
6.1
Description Reset Function
Reset
Principle:
The reset function supervises the value of the regulator output voltage V_CC. The result is monitored by the status
of pin RO. A high level at pin RO means that the output voltage V_CC is above the desired reset threshold. A low
level at pin RO means that the output voltage V_CC is below the desired reset threshold. The reset function does
not work, if the supply (V_FB) voltage is below 1 V.
Adjustment of reset threshold:
The reset generator consists of an internal comparator with a reset threshold V_RO,T. By adding an external resistor
divider between the output voltage V_CC and ground (GND) and connecting the point between the upper (R1) and
lower (R2) resistor to pin RTADJ the desired reset threshold V_RT (where the reset generator indicates an under
voltage) might be adjusted.
If reset function is not used please connect pin RTADJ to V_CC.
Desired
reset
threshold
=
V_RO,
T
⎛
⎝
R-----1--R--+_{---2--R-----2-⎠⎞}
=
V_RT
Operation mode (please refer to Figure 7):
The reset generator starts operating as soon as the regulator is activated by supplying the device with an input
(battery) voltage higher than the input voltage startup threshold V_S,ON.
The pin RO is low at this time.
When the regulator starts to operate, V_CC ramps up and passes the desired reset threshold. The reset delay time
t_RD is the time duration between that point and pin RO turning to high level.
The reset reaction time t_RR is the maximum duration or time, the output voltage V_CC may dip below the desired
reset threshold, before a reset is indicated and pin RO is pulled to low level. This is implemented to avoid wrong
reset triggering by short “glitches” on the output voltage V_CC. If the output voltage V_CC dips below the desired reset
threshold V_RT for more than t_RR , t_RR is also the time until pin RO is pulled below V_RO,L.
A voltage dip at the output voltage V_CC leads to a low level at pin RO under the following condition:
V_CC
<
V_RO,
⎛
T_⎝
R-----1--R--+_{---2--R-----2-⎠⎞}
(
for
t
> t_RR)
In case the pin RO is pulled to low level, it stays low for the time until the output voltage V_CC is higher than the
desired reset threshold V_RT plus the reset delay time t_RD.
Data Sheet
19
Rev. 1.0, 2013-06-19