28478-DSH-002-E Datasheet, PDF (92/195 Pages) M/A-COM Technology Solutions, Inc. – Multichannel Synchronous Communications

Memory Organization
Table 5-6. Global Configuration Descriptor (2 of 2)
Bit
Field
Name
Value
Description
1:0
PORTMAP[1:0]
0
Default.
Port 0 mapped to Channel Group 0.
Port 1 mapped to Channel Group 1.
Port 2 mapped to Channel Group 2.
Port 3 mapped to Channel Group 3.
Port 4 mapped to Channel Group 4.
Port 5 mapped to Channel Group 5.
Port 6 mapped to Channel Group 6.
Port 7 mapped to Channel Group 7.
1
Port 0 mapped to Channel Groups 0 and 1.
Port 1 mapped to Channel Groups 2 and 3.
Port 2 mapped to Channel Groups 4 and 5.
Port 3 mapped to Channel Groups 6 and 7.
2
Port 0 mapped to Channel Groups 0, 1, 2, and 3.
Port 1 mapped to Channel Groups 4, 5, 6, and 7.
3
Reserved.
5.2.1.2
Dual Address Cycle Base Pointer
MUSYCC supports 32-bit and 64-bit memory addressing. The Dual Address Cycle Base Pointer (DACBASE)
supports 64-bit memory addressing and is described in Table 5-7.
If the value of DACBASE is 0, MUSYCC initiates all memory access cycles without dual-addressing. If the value is
non-0, MUSYCC initiates all memory access cycles with dual-addressing.
For cycles without dual-addressing, MUSYCC uses the AD[31:0] signal lines to indicate the address of the memory
access. During the address phase, MUSYCC encodes the type of access cycle (e.g., read, write,...) in the
Command/Byte Enable signal lines, CBE[3:0]*. The address phase lasts one PCLK period.
For cycles with dual-addressing, MUSYCC multiplexes a 64-bit address onto the AD[31:0] signal lines and adds an
additional PCLK period to the address phase. To indicate 64-bit addressing, MUSYCC encodes the dual address
code onto the CBE[3:0]* signal lines during the first PCLK period of the address phase. MUSYCC encodes the
access type code (e.g., read, write) onto the CBE[3:0]* signal lines during the second PCLK period of the address
phase.
When MUSYCC accesses a 64-bit memory address using dual addressing, the upper 32 bits of the address are
fixed to a non-0 value from DACBASE. To change from 64-bit addressing to 32-bit addressing, the value of
DACBASE must be zeroed. Although MUSYCC is capable of initiating 64-bit addressing when in master mode, it
responds only to 32-bit access cycles without dual-addressing.
Table 5-7. Dual Address Cycle Base Pointer
Bit
Field
Name
Value
Description
31:0
DACBASE[31:0]
— Dual Address Cycle Base Pointer. A 32-bit base register when non-0 causes all MUSYCC master
operations (read/write) to use PCI Dual Address Cycle. The value in this register would be the
upper 32-bits of the 64-bit addressing.
28478-DSH-002-E
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