28478-DSH-002-E Datasheet, PDF (59/195 Pages) M/A-COM Technology Solutions, Inc. – Multichannel Synchronous Communications

Host Interface
With one MUSYCC and one host, the host can use the following:
• Assuming a PCI bus rate of 33 MHz:
33 cycles per dword – 16 cycles (16 clock rule) = 17 clock cycles between dword transfers
• Assuming a PCI bus rate of 66 MHz:
66 cycles per dword – 16 cycles (16 clock rule) = 50 clock cycles between dword transfers
Accordingly, MUSYCC's T must be:
• Assuming a PCI bus rate of 33 MHz:
17 cycles – 8 cycle (target latency) = 9 clock cycles. As T has a granularity of 8 units, T must be programmed
to 8 PCI clock cycles.
• Assuming a PCI bus rate of 66 MHz:
50 cycles – 8 cycle (target latency) = 42 clock cycles. As T has a granularity of 8 units, T must be programmed
to 40 PCI clock cycles.
2.2.6.3
Latency Computation—Burst Access
When the following is assumed:
• MUSYCC has enough internal buffering to buffer up to 4-dwords worth of information per channel before
performing a 2-dword burst cycle for every access.
• MUSYCC has a granularity of 8 for its latency timer (that is, MUSYCC is always configured to give up the bus
in equal to or less than the desired time-out).
• The system will support MUSYCC burst writes and reads.
• MUSYCC, with all 256 receive and transmit channels active, needs to move 1,024 kdwords/s, or one dword
every 0.98 µs, or 4-dword bursts every 3.92 µs. That is, 130 clock cycles between bursts for a 33-MHz PCI bus
rate, and 260 clock cycles for a 66-MHz PCI bus rate.
The following can be seen:
• The worst case time it would take each burst cycle to finish is 16 cycles (16 clock rule) + 8 cycles, target
latency = 24 clock cycles to finish, worst case.
• With one MUSYCC and one host operating at a PCI bus rate of 33 MHz:
The host has 130 cycles between bursts – 24 cycles to finish, worst case = 106 clock cycles. The host's T must
be programmed to 106 cycles – 8 cycles, target latency = 98 cycles. Rounding for granularity yields 96 cycles.
• With one MUSYCC and one host operating at a PCI bus rate of 66 MHz:
The host has 260 cycles between bursts – 24 cycles to finish, worst case = 236 clock cycles. The host's T must
be programmed to 236 cycles – 8 cycles, target latency = 228 cycles. Rounding for granularity yields
224 cycles.
• For n MUSYCC and one host operating at a PCI bus rate of 33 MHz:
The host has 130 cycles between bursts – (n x 24 cycles, worst case) – 8 clock cycles, target latency = T
cycles. Therefore, for two MUSYCC's and one host, a host's T of 24 would be sufficient; that is, 130 cycles –
(2 x 24) – 8 cycles = 74 clock cycles. Rounding for granularity equals 72 cycles.
• For n MUSYCC and one host operating at a PCI bus rate of 66 MHz:
The host has 260 cycles between bursts – (n x 24 cycles, worst case) – 8 clock cycles, target latency = T
cycles. Therefore, for two MUSYCC's and one host, a host's T of 24 would be sufficient; that is, 260 cycles –
(2 x 24) – 8 cycles = 204 clock cycles. Rounding for granularity equals 200 cycles.
On reset, the value of the latency timers are reset to 0.
28478-DSH-002-E
Mindspeed Technologies^®
46
Preliminary Information / Mindspeed Proprietary and Confidential