28478-DSH-002-E Datasheet, PDF (84/195 Pages) M/A-COM Technology Solutions, Inc. – Multichannel Synchronous Communications

Memory Organization
Figure 5-1. Shared Memory Model Per Channel Group
Group Base Pointer
Channel Group Descriptor
Tx Head Pointer – Ch 00
Tx Head Pointer – Ch.....
Tx Head Pointer – Ch 31
Tx Message Pointer – Ch 00
Tx Message Pointer – Ch .....
Tx Message Pointer – Ch 31
Rx Head Pointer – Ch 00
Rx Head Pointer – Ch ....
Rx Head Pointer – Ch 31
Rx Message Pointer – Ch 00
Rx Message Pointer – Ch ....
Rx Message Pointer – Ch 31
Tx Time Slot Map
Tx Subchannel Map
Tx Channel Config Table
Rx Time Slot Map
Rx Subchannel Map
Rx Channel Config Table
Global Configuration
Interrupt Queue
Group Configuration
Memory Protection
Message Length
Port Configuration
8478_021
Transmit Message List
Buffer Descriptor
Data Buffer Pointer
Next Message Pointer
Buffer Descriptor
Data Buffer Pointer
Next Message Pointer
Data Buffer
Data Buffer
Buffer Descriptor
Data Buffer Pointer
Next Message Pointer
Data Buffer
Receive Message List
Buffer Descriptor
Data Buffer Pointer
Next Message Pointer
Buffer Descriptor
Data Buffer Pointer
Next Message Pointer
Buffer Descriptor
Data Buffer Pointer
Next Message Pointer
Data Buffer
Data Buffer
Data Buffer
* See Table 5-19 for structure of Message Descriptor.
5.1.1
Register Map Access and Shared Memory Access
During MUSYCC’s PCI initialization, the system controller allocates a dedicated 1 MB memory range to each of
MUSYCC’s PCI functions. The memory range allocated to MUSYCC must not map to any other physical or shared
memory. Instead, the system configuration manager allocates a logical memory address range, and notifies the
system or bus controllers that any access to these ranges must result in a PCI access cycle. MUSYCC is assigned
these address ranges for each function through the PCI configuration cycle. Once configured, MUSYCC becomes
a functional PCI device on the bus.
As the host accesses MUSYCC’s allocated address ranges, it initiates the access cycles on the PCI bus. It is up to
individual MUSYCC devices on the bus to claim the access cycle. As its address ranges are accessed, MUSYCC
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