28330-DSH-002-A_15 Datasheet, PDF (77/101 Pages) M/A-COM Technology Solutions, Inc. – DS3/E3 Framer with 52 Mbps HDLC Controller

CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
4.0 Mechanical/Electrical Specifications
4.1 Timing Requirements
Figure 4-2 and Tables 4-2 through Table 4-4 illustrate the clock and data
relationships for all output and input signals. Propagation delays for the output
signals are listed below. The output signal timings are relative to the listed edge of
the clock. Clock outputs derived from clock inputs are listed with the edge as
both. This means that the delay number given applies for either edge. Input
signals should have setup and hold times with respect to the listed edge of the
given input clock. All times are listed in nanoseconds and are measured with
30 pF loading on the output pins.
Table 4-2. Clock Timing Requirements
Timing Requirements
Clock
Low Pulse Width - ρ_wl
High Pulse Width - ρ_wh
Cycle Time - t_cyc
Cycle Time
Low Pulse Width
High Pulse Width
RXCKI, DS3CKI, TXCKI
RXCKI, DS3CKI, TXCKI
RXCKI, DS3CKI, TXCKI
—
RXBCK
RXBCK
Min.
5.0
5.0
19.0
—
6 RXCKI
2 RXCKI
Typical
(44.736 MHz)
Typical
(34.368 MHz)
11.2
14.55
11.2
14.55
22.4
29.1
8 RXCKI
—
—
—
—
Units
ns
ns
ns
ns
ns
ns
Figure 4-2. Output and Input Signal Timing
Clock
Output
Signal
tpd
pwl
pwh
Input
Clock
Input
Signal
tsu
thd
100441E
Conexant
4-3