28330-DSH-002-A_15 Datasheet, PDF (39/101 Pages) M/A-COM Technology Solutions, Inc. – DS3/E3 Framer with 52 Mbps HDLC Controller

CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
2.0 Functional Description
2.3 Transmitter Operation
HDLC mode is selected by setting the ParaEn bit of the Feature Control
Register high and the DisPPDL bit of the PPDL Control Register low. Operation
is controlled by the SNDMSG and SNDFCS pins. If no message is in progress,
idle flags (01111110) are continuously transmitted in the data payload. Setting
SNDMSG high initiates message transmission. Data bytes and control signals are
provided in response to the rising edge of the TXBCK/TXGAPCK pin and are
sampled internally after the falling edge. The data and controls should be held for
a full period. The LSB of the transmitted bytes is applied to TDAT[0] and the
MSB to TDAT[7]; transmission is LSB first. The transmitter performs automatic
zero stuffing for transparency and FCS calculation for the data. The message
must be an integral number of bytes in length. The FCS is 16 or 32 bits in length
depending on the setting of the 32-bit CRC Select bit [CRC32;CR05.2] in the
PPDL Control Register. If this bit is low, a 16-bit FCS is calculated with the
polynomial:
x¹⁶+x¹²+x⁵+1
If the CRC32 bit is high, a 32-bit FCS is calculated. SNDFCS must be high
for four cycles of the transmit byte clock and the FCS is calculated with the
polynomial:
x³²+x²⁶+x²³+x²²+x¹⁶+x¹²+x¹¹+x¹⁰+x⁸+x⁷ +x⁵+x⁴+x²+x+1
The FCS is transmitted by setting both the SNDMSG and SNDFCS pins high
after the last data byte has been transmitted. An abort sequence may be
transmitted by setting SNDFCS high while SNDMSG is set low. Timing for the
transmit operation is shown in Figure 2-8.
Figure 2-8. PPDL Transmitter Timing
TXCKI
TXBCK/TXGAPCK
TDAT[7:0]
Data
SNDMSG
SNDFCS
Data
100441E
Conexant
2-17