M21050_17 Datasheet, PDF (47/70 Pages) M/A-COM Technology Solutions, Inc. – Duplex Quad (Octal) Multi-Rate CDR (1.0 Gbps - 3.2 Gbps)

Registers
2.2.9
Jitter Reduction Control
Table 2-34. Jitter Reduction Control (Jitter_reduc_N: Address MAh)
Bits
Type
Default
Label
Description
7:6
R/W
5
R/W
01b
MSPD internal
0b
lowjitter
4:0
R/W
N/A
MSPD internal
N/A
When data-rate is in the range (2.45 Gbps - 2.55 Gbps)/DRD, setting
this bit to 1b will reduce output jitter (DRD is data-rate divider).
1b: Reduce output jitter
0b: Normal operation
Note: This bit should be set to 1b for InfiniBand, SONET STS-N, PCI
Express, and Gigabit Ethernet applications.
Any value may be written to this register with no effect on performance.
21050-DSH-001-F
Mindspeed Technologies™
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