M21050_17 Datasheet, PDF (27/70 Pages) M/A-COM Technology Solutions, Inc. – Duplex Quad (Octal) Multi-Rate CDR (1.0 Gbps - 3.2 Gbps)

Functional Description
Table 1-16. High-Speed Signal Pins (2 of 2)
Pin Name
Function
DinB2P
DinB2N
DinB3P
DinB3N
VddTB0/1
VddTB2/3
DoutB0P
DoutB0N
DoutB1P
DoutB1N
DoutB2P
DoutB2N
DoutB3P
DoutB3N
Serial positive data input for channel 2
Serial negative data input for channel 2
Serial positive data input for channel 3
Serial negative data input for channel 3
Termination pin for DinB [1:0]
Termination pin for DinB [3:2]
Serial positive data output for channel 0
Serial negative data output for channel 0
Serial positive data output for channel 1
Serial negative data output for channel 1
Serial positive data output for channel 2
Serial negative data output for channel 2
Serial positive data output for channel 3
Serial negative data output for channel 3
Termination
50Ω pull up to VddTB2/3
50Ω pull up to VddTB2/3
50Ω pull up to VddTB2/3
50Ω pull up to VddTB2/3
Terminate to AVdd_Core
Terminate to AVdd_Core
50Ω pull up AVdd_I/O
50Ω pull up AVdd_I/O
50Ω pull up AVdd_I/O
50Ω pull up AVdd_I/O
50Ω pull up AVdd_I/O
50Ω pull up AVdd_I/O
50Ω pull up AVdd_I/O
50Ω pull up AVdd_I/O
Type
Input
Input
Input
Input
Input Termination
Input Termination
Output
Output
Output
Output
Output
Output
Output
Output
Table 1-17. Control, Interface, and Alarm Pins
Pin Name
Function
MF0
MF1
MF2
MF3
MF4
MF5
MF6
MF7
CTRL_Mode
Out_Mode
xRST
xJTAG_En
xRegu_En
RefClkP
RefClkN
xAlarmA
xAlarmB
Multifunction pin for hardwired mode, and two-wire interface
Multifunction pin for hardwired mode, and two-wire interface
Multifunction pin for hardwired mode, and two-wire interface
Multifunction pin for hardwired mode, and two-wire interface
Multifunction pin for hardwired mode, two-wire interface, and JTAG
Multifunction pin for hardwired mode, two-wire interface, and JTAG
Multifunction pin for hardwired mode, and JTAG
Multifunction pin for hardwired mode, and JTAG
Enable hardwired mode or two-wire interface (1b = hardwired)
Selects output data format (0b = PCML)
Reset pin (L = reset)
JTAG testing control pin (L = enable)
Internal voltage regulator control pin (L = enable)
Reference clock positive input
Reference clock negative input
A-side loss of activity/lock alarm
B-side loss of activity/lock alarm
Default
Internal pull up
Internal pull up
Internal pull up
Internal pull up
Internal pull up
Internal pull up
Internal pull up
Internal pull up
Internal pull up
Internal pull down
Internal pull up
Internal pull down
Internal pull up
Internal pull down
Internal pull down
No internal pull up/down
No internal pull up/down
Type
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
I - AC coupled
I - AC coupled
O - open drain
O - open drain
21050-DSH-001-F
Mindspeed Technologies™
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Mindspeed Proprietary and Confidential