28973-DSH-001-A Datasheet, PDF (40/119 Pages) M/A-COM Technology Solutions, Inc. – Single-Chip SDSL/HDSL Transceiver

2.0 Functional Description
2.4 Channel Unit Interface
RS8973
Single-Chip SDSL/HDSL Transceiver
2.4 Channel Unit Interface
The quaternary signals of the channel unit interface have four modes which are
programmable through bits 0 and 1 of the Channel Unit Interface Modes Register
[cu_interface_modes; 0x06]. They are serial sign-bit first, serial magnitude-bit
first, parallel master, and parallel slave.
In serial mode, a Bit-Rate Clock (BCLK) is output at twice the symbol rate.
The sign and magnitude bits of the receive data are output through RDAT on the
rising edge of BCLK. The sign and magnitude bits of the transmit data are
sampled on the falling edge of BCLK at the TDAT input. The sign bit is
transferred first, followed by the magnitude bit of a given symbol in sign-bit first
mode, while the opposite occurs in magnitude-bit first mode. The clock
relationships for serial sign-bit first mode are illustrated in Figure 2-6.
Figure 2-6. Serial Sign-Bit First Mode
BCLK
Bit-Rate Clock
QCLK
RDAT
Sign₀
Magnitude₀
Sign₁
Magnitude₁
Sign₂
TDAT
Sign₀
Magnitude₀
Sign₁
Magnitude₁
Sign₂
In parallel master mode, the sign and magnitude receive data is output through
RQ[1] and RQ[0], respectively, on the rising edge of QCLK. The quaternary
transmit data is sampled on the falling edge of QCLK. This clock and data
relationship is illustrated in Figure 2-7.
Figure 2-7. Parallel Master Mode
QCLK
RQ[1]/TQ[1]
Sign₀
Sign₁
Sign₂
RQ[0]/TQ[0]
Magnitude₀
Magnitude₁
Magnitude₂
2-16
Conexant
N8973DSD
Preliminary Information