28236-DSH-001-B_15 Datasheet, PDF (349/443 Pages) M/A-COM Technology Solutions, Inc. – ATM ServiceSAR Plus with xBR Traffic Management

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
14.0 CN8236 Registers
14.6 Counters and Status Registers
This register contains the interrupt enables that correspond to the status in the HOST_ISTAT1 register. The
assertion of the HRST* system reset pin clears all of the HOST_IMASK1 interrupt enables.
Table 14-6. 0x1d4—Host Interrupt Mask Register 1 (HOST_IMASK1)
Bit
Field
Size
Name
Description
31
30
29
28–27
26
25
24
23–16
15
14
13
12
11
10
9–3
2
1
0
1
EN_PCI_BUS_ERROR
1
EN_AALx_STAT
1
EN_TX_DISCARD
2
Reserved
1
EN_DMA_AFULL
1
EN_FR_PAR_ERR
1
EN_FR_SYNC_ERR
8
Reserved
1
EN_RSQUEUE_FULL
1
EN_RSM_OVFL
1
EN_RSM_HS_FULL
1
EN_RSM_LS_FULL
1
EN_RSM_HF_EMPT
1
EN_RSM_LF_EMPT
7
Reserved
1
EN_SEG_UNFL
1
EN_SEG_HS_FULL
1
EN_SEG_LS_FULL
Enables interrupt when PCI_BUS_ERROR status is a logic 1.
Enables interrupt when HOST_ISTAT1 (AALx_STAT) is a logic 1.
Enables interrupt when HOST_ISTAT1 (TX_DISCARD) is a logic 1.
Set to 0.
Enabled interrupt when DMA_AFULL status is a logic 1.
Enables interrupt when FR_PAR_ERR status is a logic 1.
Enables interrupt when FR_SYNC_ERR status is a logic 1.
Set to 0.
Enables interrupt when RSQUEUE_FULL status is a logic 1.
Enables interrupt when RSM_OVFL status is a logic 1.
Enables interrupt when RSM_HS_FULL status is a logic high.
Enables interrupt when RSM_LS_FULL status is a logic high.
Enables interrupt when RSM_HF_EMPT status is a logic high.
Enables interrupt when RSM_LF_EMPT status is a logic high.
Set to 0.
Enables interrupt when SEG_UNFL status is a logic high.
Enables interrupt when SEG_HS_FULL status is a logic high.
Enables interrupt when SEG_LS_FULL status is a logic high.
28236-DSH-001-B
Mindspeed Technologies™
14-33