28236-DSH-001-B_15 Datasheet, PDF (260/443 Pages) M/A-COM Technology Solutions, Inc. – ATM ServiceSAR Plus with xBR Traffic Management

10.0 Local Processor Interface
10.1 Overview
CN8236
ATM ServiceSAR Plus with xBR Traffic Management
The processor interface is a generic synchronous interface based on the Intel
i960CA 32-bit architecture and is completely compatible with the i960CA/CF
and the new i960Jx processors. Other synchronous and asynchronous processors
(for example, from Motorola, AMD, IDT) can be interfaced using external
circuitry. The only requirement is that the processor have a 32-bit bus and that the
control signals be synchronized to SYSCLK.
To access the CN8236 SAR-shared memory or control registers, the processor
must arbitrate with the CN8236 for access to the memory controller. Due to the
requirements of reassembly and segmentation access to SRAM and the
implications of PCI bus utilization, the local processor has the lowest priority in
the memory arbitration scheme. Since the local processor is typically used for low
bandwidth supervision and maintenance functions, this should be acceptable.
When the local processor accesses the CN8236’s control registers, internal
SRAM, or SAR-shared memory, a local processor memory request is generated
internal to the CN8236. The memory arbiter then coordinates this request with
requests from other memory consumers and grants the memory bus to the local
processor at the appropriate time. The local processor is held off during this
process by the insertion of a variable number of wait states, accomplished by the
i960 withholding READY* or RDYRCV*. Once the local processor is granted
the memory system, the transceivers are enabled to allow the local processor’s
address and data to access the SRAM or control registers. The conclusion of the
data transaction is signaled by the assertion of PRDY*. Wait states can inserted by
the processor at any time by asserting PWAIT*. The last data cycle in a burst is
indicated by the PBLAST* signal. In this manner, non-i960 processor half-speed
buses or slow transceivers can be accounted for.
The LP_BWAIT bit in the CONFIG0 register automatically adds a single wait
state between the first access in a burst and subsequent accesses. This can be used
to simplify the design of memory controllers for processors that do not produce a
wait output and which require more time between data cycles in a burst.
10-2
Mindspeed Technologies™
28236-DSH-001-B