28236-DSH-001-B_15 Datasheet, PDF (321/443 Pages) M/A-COM Technology Solutions, Inc. – ATM ServiceSAR Plus with xBR Traffic Management

CN8236
ATM ServiceSAR Plus with xBR Traffic Management
14.0 CN8236 Registers
14.2 System Registers
0x0c—System Status Register (SYS_STAT)
The System Status register provides read-only system status. This register reflects the device ID and version
information for the part, and pin-programmable options that otherwise might not be visible to the processors. It
also contains expanded information for the status located in the HOST_ISTAT0 and LP_ISTAT0 registers.
Bit
31–17
16–12
Field
Size
15
5
Name
Reserved
PCI_BUS_STATUS
[4:0]
11
1
RAMMODE
10
1
PROCMODE
9, 8
2
FRCFG[1:0]
7–4
4
VERSION [3:0]
3–0
4
DEVICE[3:0]
Description
Not implemented at this time.
The status bits are as follows:
4 = Target Abort
3 = Master Abort
2 = Parity Error
1 = Interface Disabled
0 = Internal Failure
Reflects corresponding error bits in the PCI Configuration register. Bits are
reset by either a write to the PCI Configuration register by the host, or by
setting CONFIG0 (PCI_ERR_RESET) bit.
Reflects the state of the RAMMODE input pin.
Reflects the state of the PROCMODE input pin.
Reflects the state of the FRCFG[1:0] input pins.
Version number for the CN8236: Rev A = 0 and Rev B = 2.
Device ID for the CN8236; set to 4.
28236-DSH-001-B
Mindspeed Technologies™
14-5