M02014 Datasheet, PDF (18/19 Pages) M/A-COM Technology Solutions, Inc. – CMOS Transimpedance Amplifier with AGC for Fiber Optic Networks up to 2.5 Gbps

5.0 Die Specification
Figure 5-1. Bare Die Layout
NOTES:
Process technology: CMOS, Silicon Nitride passivation
Die thickness: 300 µm
Pad metallization: Aluminium
Die size: 880 µm x 1090
Pad openings (except PinA): 86 µm across flats
PinA pad: 70 µm across flats (70 µm x 70 µm)
Pad Centers in µm referenced to center of device
Pad
Number
Pad
X
Y
1
AGC
–329
–76
2 ⁽¹⁾
V_CC
–329
–228
3
PINK
–124
–434
4
PINA
124
–434
5 ⁽¹⁾
V_CC
329
–228
6
MON
329
–76
7
DOUT
329
76
8 ⁽¹⁾
DOUTGND
329
228
9c ^{(1, 2)}
GND
329
360
9b ^{(1, 2)}
GND
255
434
9a ^{(1, 2)}
GND
124
434
10a ^{(1, 2)}
GND
–124
434
10b ^{(1, 2)}
GND
–255
434
10c ^{(1, 2)}
GND
–329
360
11 ⁽¹⁾
DOUTGND
–329
228
12
DOUT
–329
76
NOTES:
1. It is only necessary to bond one V_CC pad and one
GND pad. However, bonding one of each pad (if
available) on each side of the die is encouraged for
improved performance in noisy environments.
2. Each location is an acceptable bonding location.
02014-DSH-001-D
Mindspeed Technologies^®
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