LTC3770 Datasheet, PDF (9/24 Pages) Linear Technology – Synchronous Controller with Margining, Tracking and PLL

LTC3770
PI FU CTIO S (UH Package/G Package)
V_ON (Pin 31/Pin 2): On-Time Voltage Input. Connecting
this pin to the output voltage makes the on-time propor-
tional to V_OUT. The comparator input defaults to 0.6V when
the pin is grounded and defaults to 4.8V when the pin is
tied to INTV_CC.
PGOOD (Pin 32/Pin 3): Power Good Output. Open drain
logic output that is pulled to ground when the output
voltage is not within ±10% of the regulation point, after the
internal 25µs power bad mask timer expires.
Exposed Pad (Pin 33) UH Package: Signal Ground. Must
be soldered to the PCB ground for electrical contact and
optimum thermal performance.
W
FU CTIO AL DIAGRA (UH Package)
PLLFLTR
12
PLL-SYNC
PLLIN 13
V_OUT
31 V_ON
0.6V 4.8V
R_ON
7 I_ON
29 FCB
t_ON
=
V_VON
I_ION
(10pF)
R
15
R
V_INSNS
0.6V
R
–+
F
R
SQ
R4
MPGM 10
–
1.18V
+
20k
+
I_CMP
I_REV
–
2.0V
MARGIN0
6
MARGIN1
5
V_RNG
1
0.5V
×
(0.5~2)
3.3µA
FOLDBACK
DISABLED
AT START-UP*
V_IN
0.6V
1
REF
240k
Q2 Q4
I_THB
Q6
Q1
EA
12K
V_REFOUT
9
R3
V_REFIN
8
SS
–+
80% • V_REFIN
3 I_{TH RC} ^CC1
INTV_CC
1µA
5V
REG
Z0 28
Z1 17
Z2 18
FCNT
ON _SWITCH
LOGIC
AND
ANTI-
SHOOT
THROUGH
RUN
OV
0.25V
V_IN
14 V_{IN +}
C_IN
BOOST
27
TG
26
SW
25
SENSE⁺
24
SENSE^–
23
DRV_CC
20
BG
21
INTV_CC
19
C_B
D_B
C_VCC
PGND
22
32
PGOOD
Z_VIN
16
M1
L1
+
C_OUT
M2
R_SENSE
(OPTIONAL)*
V_OUT
OV
UV
RUN
–+
1.5V
INTV_CC
1.4µA
R2
10K
V_FB
2
R1
SGND
10K
4
SW
SENSE⁺
90K
BG
M2
SENSE^–
PGND
*CONNECTION W/O
SENSE RESISTOR
RUN 30
11 TRACK/SS ^CSS
3770f
9