LTC3770 Datasheet, PDF (19/24 Pages) Linear Technology – Synchronous Controller with Margining, Tracking and PLL

LTC3770
APPLICATIO S I FOR ATIO
operating point the phase comparator output is open and
the filter capacitor C_LP holds the voltage. The LTC3770
PLLIN pin must be driven from a low impedance source
such as a logic gate located close to the pin.
The loop filter components (C_LP, R_LP) smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components C_LP and R_LP determine how fast the loop
acquires lock. Typically R_LP =10kΩ and C_LP is 0.01µF to
0.1µF.
Dead Time Control
To further optimize the efficiency, the LTC3770 gives
users some control over the dead time of the Top gate low
and Bottom gate high transition. By applying a DC voltage
on the Z0 pin, the TG low BG high dead time can be
programmed. Because the dead time is a strong function
of the load current and the type of MOSFET used, users
need to be careful to optimize the dead time for their
particular applications. Figure 11 shows the relation be-
tween the TG Low BG High Dead time by varying the Z0
voltages. For an application using LTC3770 with load
current of 5A and IR7811W MOSFETs, the dead time could
be optimized. To make sure that there is no shoot-through
under all conditions, a dead time of 70ns is selected. This
corresponds to a DC voltage about 2.6V on Z0 pin. This
voltage can easily be generated with a resistor divider off
INTV_CC.
180
160
140
120
100
80
60
40
20
0 I_OUT = 5A
IRT811W FETs
–20
0
1
2
3
4
5
Z0 VOLTAGE (V)
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Figure 11. TG Low BG High Dead Time vs Z0 Voltage
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in the circuit produce losses, four main sources
account for most of the losses in LTC3770 circuits:
1. DC I²R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause the
efficiency to drop at high output currents. In continuous
mode the average output current flows through L, but is
chopped between the top and bottom MOSFETs. If the two
MOSFETs have approximately the same R_DS(ON), then the
resistance of one MOSFET can simply be summed with the
resistances of L and the board traces to obtain the DC I²R
loss. For example, if R_DS(ON) = 0.01Ω and R_L = 0.005Ω, the
loss will range from 15mW to 1.5W as the output current
varies from 1A to 10A.
2. Transition loss. This loss arises from the brief amount
of time the top MOSFET spends in the saturated region
during switch node transitions. It depends upon the input
voltage, load current, driver strength and MOSFET
capacitance, among other factors. The loss is significant
at input voltages above 20V and can be estimated from:
Transition Loss ≅ (1.7A^–1) V_IN2 I_OUT C_RSS f
3. INTV_CC current. This is the sum of the MOSFET driver
and control currents.
4. C_IN loss. The input capacitor has the difficult job of
filtering the large RMS input current to the regulator. It
must have a very low ESR to minimize the AC I²R loss and
sufficient capacitance to prevent the RMS current from
causing additional upstream losses in fuses or batteries.
Other losses, including C_OUT ESR loss, Schottky diode D1
conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss.
When making adjustments to improve efficiency, the
input current is the best indicator of changes in efficiency.
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