LTC3615 Datasheet, PDF (9/32 Pages) Linear Technology – Dual 4MHz, 3A Synchronous Step-Down DC/DC Converter

LTC3615
Pin Functions (FE/UF)
PHASE (Pin 1/Pin 4): Phase Shift Selection. If pin is tied to
SGND, the phase between SW1 and SW2 will be 0°. Tying
PHASE to SV_IN will select 180° of phase shift. With the
PHASE pin tied to half of the SV_IN voltage, 90° of phase
shift will be selected.
V_FB2 (Pin 2/Pin 5): Voltage Feedback Input Pin for Chan-
nel 2. See V_FB1.
ITH2 (Pin 3/Pin 6): Error Amplifier Compensation of
Channel 2. See ITH1.
TRACK/SS2 (Pin 4 /Pin 7): Internal, External Soft-Start, Ex-
ternal Reference Input for Channel 2. See TRACK/SS1.
SGND (Pin 5/Pin 8): Signal Ground. All small-signal and
compensation components should connect to this ground
pin which, in turn, should be connected to PGND at one
point.
PV_IN2 (Pins 6, 7/Pins 9, 10) Channel 2 Power Supply
Input. See PV_IN1.
SW2 (Pins 8, 9/Pins 11, 12): Channel 2 Switching Node.
See SW1.
RUN2 (Pin 10/Pin 13): Enable Pin for Channel 2. See
RUN1.
RUN1 (Pin 11/Pin 14): Enable Pin for Channel 1. Forc-
ing RUN1 above the input threshold enables the output
SW1 of channel 1. Forcing both RUNx pins to ground
shuts down the LTC3615. In shutdown, all functions
are disabled and the LTC3615 draws <1µA of supply
current.
R_T/SYNC (Pin 12/Pin 15): Oscillator Frequency. This
pin provides three modes of setting the switching fre-
quency.
1. Connecting a resistor from R_T/SYNC to ground will
set the switching frequency based on the resistor
value.
2. Driving R_T/SYNC with an external clock signal will
synchronize the switcher to the applied frequency. The
slope compensation is automatically adapted to the
external clock frequency.
3. Tying this pin to SV_IN enables the internal 2.25MHz
oscillator frequency.
PGOOD2 (Pin 13/Pin 16): Power Good Output for
Channel 2. See PGOOD1.
SRLIM (Pin 14 /Pin 17): Slew Rate Limit. Slew rate on the
switch pins is programmed with the SRLIM pin:
1. Tying this pin to SGND selects maximum slew rate.
2. Minimum slew rate is selected when the pin is open.
3. Connecting a resistor from SRLIM to SGND allows the
slew rate to be continuously adjusted.
4. If SRLIM is tied to SV_IN the slew rate is set to maxi-
mum and DDR mode is enabled (see the Applications
Information section).
PGOOD1 (Pin 15/Pin 18): Power Good Output Pin for
Channel 1. The open-drain output will be pulled down to
ground when the FB1 voltage of the channel is not within
the power good voltage window. The PGOOD1 will also be
pulled down if the channel is not enabled with the RUN1
pin or an undervoltage at SV_IN is detected. In DDR mode
(SRLIM = SV_IN), the power good window moves in relation
to the actual TRACK/SS pin voltage.
SW1 (Pins 17, 16/Pins 19, 20): Channel 1 Switching
Node. Connection to the external inductor. This pin con-
nects to the drains of the internal synchronous power
MOSFET switches.
PV_IN1 (Pins 18, 19/Pins 21, 22): Channel 1 Power Supply
Inputs. These pins connect to the source of the internal
power P-channel MOSFET of channel 1. P_VIN1 and P_VIN2
are independent of each other. They may connect to equal
or lower supplies than S_VIN.
SV_IN (Pin 20/Pin 23) Signal Input Supply. This pin pow-
ers the internal control circuitry and is monitored by the
undervoltage lockout comparator.
3615f