LTC3615 Datasheet, PDF (26/32 Pages) Linear Technology – Dual 4MHz, 3A Synchronous Step-Down DC/DC Converter

LTC3615
Applications Information
C_OUT will be selected based on the ESR that is required
to satisfy the output voltage ripple requirement and the
bulk capacitance needed for loop stability. For this design,
47µF ceramic capacitors will be used with X5R or X7R
dielectric.
C_IN should be sized for a maximum current rating of:
I_RMS(MAX)
=
I_OUT1
2
+
I _OUT2
2
=
2A _RMS
Decoupling the PV_IN with two 47µF capacitors is adequate
for most applications.
Finally, it is possible to define the soft-start up time choos-
ing the proper value for the capacitor and the resistor
connected to TRACK/SS pin. If one sets minimum T_SS =
5ms and a resistor of 4.7M, the following equation can
be solved with the maximum SV_IN = 5.5V:
C_SS
=
5ms
4.7M
•
In


5.5V
5.5V – 0.6V


= 9.2nF
The standard value of 10nF and 4.7M guarantees the
minimum soft-start time of 5ms. In Figure 3, channel 1
shows the schematic for this design example.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3615:
1. A ground plane is recommended. If a ground plane
layer is not used, the signal and power grounds should
be segregated with all small signal components return-
ing to the SGND pin at one point which is then con-
nected to the PGND node at the exposed pad close to
the LTC3615
2. Connect the (+) terminal of the input capacitors, C_IN,
as close as possible to the PV_INx pins, and the (–) ter-
minal as close as possible to the exposed pad PGND.
This capacitor provides the AC current into the internal
power MOSFETs.
3. Keep the switching nodes, SWx, away from all sensitive
small signal nodes FBx, ITHx, RTSYNC, SRLIM.
4. Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. Connect the copper areas to PGND (ex-
posed pad) for best performance.
5. Connect the V_FBx pins directly to the feedback resistors.
The resistor divider must be connected between V_OUTx
and SGND.
3615f
26