LTC1403-1_12 Datasheet, PDF (9/22 Pages) Linear Technology – Serial 12-Bit/14-Bit, 2.8Msps

LTC1403-1/LTC1403A-1
PIN FUNCTIONS
A_IN+ (Pin 1): Noninverting Analog Input. A_IN+ operates
fully differentially with respect to A_IN– with a –1.25V to
1.25V differential swing with respect to A_IN– and a 0V to
V_DD common mode swing.
A_IN– (Pin 2): Inverting Analog Input. A_IN– operates fully
differentially with respect to A_IN+ with a 1.25V to –1.25V
differential swing with respect to A_IN+ and a 0V to V_DD
common mode swing.
V_REF (Pin 3): 2.5V Internal Reference. Bypass to GND
and to a solid analog ground plane with a 10µF ceramic
capacitor (or 10µF tantalum in parallel with 0.1µF ceramic).
Can be overdriven by an external reference between 2.55V
and V_DD.
GND (Pins 4, 5, 6, Exposed Pad Pin 11): Ground. These
ground pins and the exposed pad must be tied directly to
the solid ground plane under the part. Keep in mind that
analog signal currents and digital output signal currents
flow through these pins.
V_DD (Pin 7): 3V Positive Supply. This single power pin
supplies 3V to the entire chip. Bypass to GND and to a
solid analog ground plane with a 10µF ceramic capacitor
(or 10µF tantalum in parallel with 0.1µF ceramic). Keep in
mind that internal analog currents and digital output signal
currents flow through this pin. Care should be taken to
place the 0.1µF bypass capacitor as close to Pins 6 and
7 as possible.
SDO (Pin 8): Three-State Serial Data Output. Each of
output data words represents the difference between
A_IN+ and A_IN– analog inputs at the start of the previous
conversion. The output format is 2’s complement.
SCK (Pin 9): External Clock Input. Advances the conver-
sion process and sequences the output data on the rising
edge. Responds to TTL (≤3V) and 3V CMOS levels. One
or more pulses wake from sleep.
CONV (Pin 10): Convert Start. Holds the analog input signal
and starts the conversion on the rising edge. Responds
to TTL (≤3V) and 3V CMOS levels. Two pulses with SCK
in fixed high or fixed low state start Nap mode. Four or
more pulses with SCK in fixed high or fixed low state start
Sleep mode.
BLOCK DIAGRAM
10µF 3V
A_IN+
A_IN–
10µF
LTC1403A-1
7 _VDD
1+
S&H
2–
14-BIT ADC
14
3 ^VREF
GND
4
2.5V
REFERENCE
5
6
11
EXPOSED PAD
THREE-
STATE
SERIAL
OUTPUT
PORT
8 SDO
TIMING
LOGIC
10 CONV
9 SCK
14031 BD
14031fc
9