LTC1403-1_12 Datasheet, PDF (1/22 Pages) Linear Technology – Serial 12-Bit/14-Bit, 2.8Msps

LTC1403-1/LTC1403A-1
Serial 12-Bit/14-Bit, 2.8Msps
Sampling ADCs with Shutdown
FEATURES
n _{2.8Msps Conversion Rate}
n _{Low Power Dissipation: 14mW}
n _{3V Single Supply Operation}
n _{2.5V Internal Bandgap Reference can be Overdriven}
n _{3-Wire Serial Interface}
n _{Sleep (10µW) Shutdown Mode}
n _{Nap (3mW) Shutdown Mode}
n _{80dB Common Mode Rejection}
n _{±1.25V Bipolar Input Range}
n _{Tiny 10-Lead MSE Package}
APPLICATIONS
n _{Communications}
n _{Data Acquisition Systems}
n _{Uninterrupted Power Supplies}
n _{Multiphase Motor Control}
n _{Multiplexed Data Acquisition}
DESCRIPTION
The LTC^®1403-1/LTC1403A-1 are 12-bit/14-bit, 2.8Msps
serial ADCs with differential inputs. The devices draw only
4.7mA from a single 3V supply and come in a tiny 10-lead
MSE package. A Sleep shutdown feature lowers power
consumption to 10µW. The combination of speed, low
power and tiny package makes the LTC1403-1/LTC1403A‑1
suitable for high speed, portable applications.
The 80dB common mode rejection allows users to elimi-
nate ground loops and common mode noise by measuring
signals differentially from the source.
The devices convert –1.25V to 1.25V bipolar inputs
differentially. The absolute voltage swing for A_IN+ and
A_IN– extends from ground to the supply voltage.
The serial interface sends out the conversion results during
the 16 clock cycles following CONV↑ for compatibility with
standard serial interfaces. If two additional clock cycles
for acquisition time are allowed after the data stream in
between conversions, the full sampling rate of 2.8Msps
can be achieved with a 50.4MHz clock.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
BLOCK DIAGRAM
10µF 3V
A_IN+
A_IN–
10µF
LTC1403A-1
7 _VDD
1+
S&H
2–
14-BIT ADC
14
3 ^VREF
GND
4
2.5V
REFERENCE
5
6
11
EXPOSED PAD
THREE-
STATE
SERIAL
OUTPUT
PORT
8 SDO
TIMING
LOGIC
10 CONV
9 SCK
14031 TA01a
THD, 2nd and 3rd vs Input
Frequency for Differential Input
Signals
–44
–50
–56
–62
–68
–74
THD 3rd
–80
–86
2nd
–92
–98
–104
0.1
1
10
FREQUENCY (MHz)
100
14031 TA01b
14031fc
1