LTC3901_15 Datasheet, PDF (8/16 Pages) Linear Technology – Secondary Side Synchronous Driver for Push-Pull and Full-Bridge Converters

LTC3901
APPLICATIO S I FOR ATIO
The timeout period is determined predominantly by the
external R_TMR and C_TMR values and is independent of the
V_CC voltage. This independence is achieved by making the
timeout threshold a ratio of V_CC. The ratio is 0.2x, set
internally by R1 and R2 (see Figure 3). The Timeout period
should be programmed to around 1 period of the primary
switching frequency using the following formula:
TIMEOUT = 0.2 • R_TMR • C_TMR + 0.27E-06
To reduce error in the timeout setting due to the discharge
time, select C_TMR between 100pF and 1000pF. Start with
a C_TMR around 470pF and then calculate the required
R_TMR. C_TMR should be placed as close as possible to the
LTC3901 with minimum PCB trace between C_TMR, the
TIMER pin and GND. This is to reduce any ringing caused
by the PCB trace inductance when C_TMR discharges. This
ringing may introduce error to the timeout setting.
The timer input also includes a current sinking clamp
circuit (Z_TMR in Figure 3) that clamps this pin to about
0.5 • V_CC if there is missing SYNC/timer reset pulse. This
clamp circuit prevents the timer capacitor from getting
fully charged up to the rail, which would result in a longer
discharge time. The current sinking capability of the circuit
is around 1mA.
The timeout function can be disabled by connecting the
timer pin to GND.
Synchronization Sequence
A typical push-pull converter cycle always turns off ME
and MF alternately. The SYNC input should alternate
between a positive and negative pulse. The LTC3901
includes a sequential logic to monitor the SYNC input
pulses. If after one positive pulse the SYNC comparator
receives another positive pulse, the LTC3901 sequential
logic shuts off both drivers until a negative pulse appears.
The same applies to double negative pulses; the driver will
turn on only after receiving a positive pulse. This is to
protect the external components in situations where only
one polarity of the SYNC pulse is present and the corre-
sponding driver remains on. Figure 5 shows the SYNC
double pulse operation.
The LTC3901 has two separate SYNC comparators (S⁺ and
S^– in the Block Diagram) to detect the positive and nega-
tive pulses. The threshold voltages of both comparators
are designed to be of the same magnitude but opposite in
8
polarity. In some situations, for example during power-up
or power-down, the SYNC pulse magnitude may be low
(slightly higher or lower than the threshold of the compara-
tors). This can cause only one of the SYNC comparators to
trip. This also appears as a double pulse to the sequential
logic and both drivers will be shut off.
Current Sense
The differential input current sense comparators, ISE and
ISF (Figure 6), are used for sensing the voltage across the
drain-to-source terminal of the MOSFET through the CSX⁺
and CSX^– pins. There are two sets of comparator inputs,
one for each MOSFET (ME and MF). If the inductor current
reverses into the MOSFET causing CSX⁺ to rise above
CSX^– by more than 10.5mV, the LTC3901 turns off the
respective MOSFET. This comparator is used to prevent
inductor reverse current buildup during power-down or
Burst Mode operation, which may cause damage to the
MOSFETs. The 10.5mV input threshold has a positive
temperature coefficient, which closely matches the TC of
the external MOSFET R_DS(ON). The current sense com-
parator is only active 250ns after the respective driver
SECOND NEGATIVE SYNC PULSE,
BOTH ME AND MF PULL LOW
SYNC
0V
ME
MF
EXPECTED POSITIVE SYNC PULSE,
MF PULLS HIGH
3901 F05
Figure 5. SYNC Double Pulse Operation
T1
R_CSE1 ^RCSE2
CSE⁺
ISE
6
ME
R_CSE3
10.5mV
CSE^–
5
–+
Z_CSE
11V
R_CSF1
MF
R_CSF3
LTC3901
CSF⁺
ISF
11
10.5mV
CSF^–
12
–+
R_CSF2
Z_CSF
11V
3901 F06
Figure 6. Current Sense Circuit
3901f