LTC3728_15 Datasheet, PDF (8/36 Pages) Linear Technology – Dual, 550kHz, 2-Phase Synchronous Step-Down Switching Regulator

LTC3728
TYPICAL PERFORMANCE CHARACTERISTICS
Undervoltage Lockout
vs Temperature
3.50
3.45
3.40
3.35
3.30
3.25
3.20
–50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
3728 G29
Shutdown Latch Thresholds
vs Temperature
4.5
4.0
LATCH ARMING
3.5
3.0
LATCHOFF
THRESHOLD
2.5
2.0
1.5
1.0
0.5
0
–50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
3728 G30
PIN FUNCTIONS G Package/UH Package
RUN/SS1, RUN/SS2 (Pins 1, 15/Pins 28, 13): Combination
of soft-start, run control inputs and short-circuit detection
timers. A capacitor to ground at each of these pins sets the
ramp time to full output current. Forcing either of these pins
back below 1.0V causes the IC to shut down the circuitry
required for that particular controller. Latchoff overcurrent
protection is also invoked via this pin as described in the
Applications Information section.
SENSE1⁺, SENSE2⁺ (Pins 2, 14/Pins 30, 12): The (+)
Input to the Differential Current Comparators. The I_TH pin
voltage and controlled offsets between the SENSE^– and
SENSE⁺ pins in conjunction with R_SENSE set the current
trip threshold.
SENSE1^–, SENSE2^– (Pins 3, 13/Pins 31, 11): The (–)
Input to the Differential Current Comparators.
V_OSENSE1, V_OSENSE2 (Pins 4, 12/Pins 1, 9): Receives the
remotely-sensed feedback voltage for each controller from
an external resistive divider across the output.
PLLFLTR (Pin 5/Pin 2): The Phase-Locked Loop’s Lowpass
Filter is Tied to This Pin. Alternatively, this pin can be driven
with an AC or DC voltage source to vary the frequency of
the internal oscillator.
PLLIN (Pin 6/Pin 3): External Synchronization Input to
Phase Detector. This pin is internally terminated to SGND
with 50kΩ. The phase-locked loop will force the rising
top gate signal of controller 1 to be synchronized with
the rising edge of the PLLIN signal.
FCB (Pin 7/Pin 4): Forced Continuous Control Input.
This input acts on both controllers and is normally used
to regulate a secondary winding. Pulling this pin below
0.8V will force continuous synchronous operation.
I_TH1, I_TH2 (Pins 8, 11/Pins 5, 8): Error Amplifier Output
and Switching Regulator Compensation Point. Each as-
sociated channels’ current comparator trip point increases
with this control voltage.
SGND (Pin 9/Pin 6): Small Signal Ground common to
both controllers, must be routed separately from high
current grounds to the common (–) terminals of the
C_OUT capacitors.
3.3V_OUT (Pin 10/Pin 7): Output of a linear regulator ca-
pable of supplying 10mA DC with peak currents as high
as 50mA.
NC (Pins 10, 16, 29, 32 UH Package Only): No Connect.
PGND (Pin 20/Pin 19): Driver Power Ground. Connects to
the sources of bottom (synchronous) N-channel MOSFETs,
anodes of the Schottky rectifiers and the (–) terminal(s)
of C_IN.
3728fg
8