LTC3728_15 Datasheet, PDF (18/36 Pages) Linear Technology – Dual, 550kHz, 2-Phase Synchronous Step-Down Switching Regulator

LTC3728
APPLICATIONS INFORMATION
the maximum RMS current of one channel must be used.
The maximum RMS capacitor current is given by:
( ) _{CIN Required IRMS IMAX} ^V_OUT
V_IN
V_OUT
V_IN
^1/2
This formula has a maximum at V_IN = 2V_OUT, where
I_RMS = I_OUT/2. This simple worst case condition is com-
monly used for design because even significant deviations
do not offer much relief. Note that capacitor manufacturer’s
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the capaci-
tor, or to choose a capacitor rated at a higher temperature
than required. Several capacitors may also be paralleled
to meet size or height requirements in the design. Always
consult the manufacturer if there is any question.
The benefit of the LTC3728 multiphase can be calculated by
using the equation above for the higher power controller
and then calculating the loss that would have resulted if
both controller channels switch on at the same time. The
total RMS power lost is lower when both controllers are
operating due to the interleaving of current pulses through
the input capacitor’s ESR. This is why the input capacitor’s
requirement calculated above for the worst-case controller
is adequate for the dual controller design. Remember that
input protection fuse resistance, battery resistance and PC
board trace resistance losses are also reduced due to the
reduced peak currents in a multiphase system. The overall
benefit of a multiphase design will only be fully realized
when the source impedance of the power supply/battery
is included in the efficiency testing. The drains of the
two top MOSFETs should be placed within 1cm of each
other and share a common C_IN(s). Separating the drains
and C_IN may produce undesirable voltage and current
resonances at V_IN.
The selection of C_OUT is driven by the required effective
series resistance (ESR). Typically, once the ESR require-
ment is satisfied the capacitance is adequate for filtering.
The output ripple (ΔV_OUT) is determined by:

V_OUT


I_L

 ^ESR
+
1
8fC_OUT


Where f = operating frequency, C_OUT = output capacitance,
and ΔI_L= ripple current in the inductor. The output ripple is
highest at maximum input voltage since ΔI_L increases with
input voltage. With ΔI_L = 0.3I_OUT(MAX) the output ripple
will typically be less than 50mV at max V_IN assuming:
C_OUT Recommended ESR < 2 R_SENSE
and C_OUT > 1/(8fR_SENSE)
The first condition relates to the ripple current into the ESR
of the output capacitance while the second term guarantees
that the output capacitance does not significantly discharge
during the operating frequency period due to ripple current.
The choice of using smaller output capacitance increases
the ripple voltage due to the discharging term but can be
compensated for by using capacitors of very low ESR to
maintain the ripple voltage at or below 50mV. The I_TH pin
OPTI-LOOP compensation components can be optimized
to provide stable, high performance transient response
regardless of the output capacitors selected.
Manufacturers such as Nichicon, United Chemicon and
Sanyo can be considered for high performance through-
hole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo has the lowest (ESR)(size)
product of any aluminum electrolytic at a somewhat
higher price. An additional ceramic capacitor in parallel
with OS-CON capacitors is recommended to reduce the
inductance effects.
In surface mount applications multiple capacitors may
need to be used in parallel to meet the ESR, RMS current
handling and load step requirements of the application.
Aluminum electrolytic, dry tantalum and special polymer
capacitors are available in surface mount packages. Special
polymer surface mount capacitors offer very low ESR but
3728fg
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