LTC3727A-1 Datasheet, PDF (8/32 Pages) Linear Technology – High Efficiency, 2-Phase Synchronous Step-Down Switching Regulators

LTC3727A-1
PI FU CTIO S
RUN/SS1, RUN/SS2 (Pins 1, 15): Combination of Soft-
Start, Run Control Inputs. A capacitor to ground at each of
these pins sets the ramp time to full output current.
Forcing either of these pins back below 1.0V causes the IC
to shut down the circuitry required for that particular
controller.
SENSE1⁺, SENSE2⁺ (Pins 2, 14): The (+) Input to the
Differential Current Comparators. The I_TH pin voltage and
controlled offsets between the SENSE^– and SENSE⁺ pins
in conjunction with R_SENSE set the current trip threshold.
SENSE1^–, SENSE2^– (Pins 3, 13): The (–) Input to the
Differential Current Comparators.
V_OSENSE1, V_OSENSE2 (Pins 4, 12): Receives the remotely-
sensed feedback voltage for each controller from an
external resistive divider across the output.
PLLFLTR (Pin 5): The phase-locked loop’s lowpass filter
is tied to this pin. Alternatively, this pin can be driven with
an AC or DC voltage source to vary the frequency of the
internal oscillator.
PLLIN (Pin 6): External Synchronization Input to Phase
Detector. This pin is internally terminated to SGND with
100kΩ. The phase-locked loop will force the rising top
gate signal of controller 1 to be synchronized with the
rising edge of the PLLIN signal.
FCB (Pin 7): Forced Continuous Control Input. This input
acts on both controllers and is normally used to regulate
a secondary winding. Pulling this pin below 0.8V will
force continuous synchronous operation. Do not leave
this pin floating.
I_TH1, I_TH2 (Pins 8, 11): Error Amplifier Outputs and Switch-
ing Regulator Compensation Points. Each associated chan-
nels’ current comparator trip point increases with this
control voltage.
SGND (Pin 9): Small Signal Ground. Common to both
controllers; must be routed separately from high current
grounds to the common (–) terminals of the C_OUT
capacitors.
3.3V_OUT (Pin 10): Linear Regulator Output. Capable of
supplying 10mA DC with peak currents as high as 50mA.
PGND (Pin 20): Driver Power Ground. Connects to the
sources of bottom (synchronous) N-channel MOSFETs, an-
odes of the Schottky rectifiers and the (–) terminal(s) of C_IN.
INTV_CC (Pin 21): Output of the Internal 7.5V Linear Low
Dropout Regulator and the EXTV_CC Switch. The driver and
control circuits are powered from this voltage source. Must
be decoupled to power ground with a minimum of 4.7µF
tantalum or other low ESR capacitor.
EXTV_CC (Pin 22): External Power Input to an Internal
Switch Connected to INTV_CC. This switch closes and
supplies V_CC power, bypassing the internal low dropout
regulator, whenever EXTV_CC is higher than 7.3V. See
EXTV_CC connection in Applications section. Do not exceed
8.5V on this pin.
BG1, BG2 (Pins 23, 19): High Current Gate Drives for
Bottom (Synchronous) N-Channel MOSFETs. Voltage
swing at these pins is from ground to INTV_CC.
V_IN (Pin 24): Main Supply Pin. A bypass capacitor should
be tied between this pin and the signal ground pin.
BOOST1, BOOST2 (Pins 25, 18): Bootstrapped Supplies
to the Top Side Floating Drivers. Capacitors are connected
between the boost and switch pins and Schottky diodes
are tied between the boost and INTV_CC pins. Voltage swing
at the boost pins is from INTV_CC to (V_IN + INTV_CC).
SW1, SW2 (Pins 26, 17): Switch Node Connections to
Inductors. Voltage swing at these pins is from a Schottky
diode (external) voltage drop below ground to V_IN.
TG1, TG2 (Pins 27, 16): High Current Gate Drives for Top
N-Channel MOSFETs. These are the outputs of floating
drivers with a voltage swing equal to INTV_CC – 0.5V
superimposed on the switch node voltage SW.
PGOOD (Pin 28): Open-Drain Logic Output. PGOOD is
pulled to ground when the voltage on either V_OSENSE pin is
not within ±7.5% of its set point.
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