LTC3543 Datasheet, PDF (8/16 Pages) Linear Technology – 600mA Synchronous Step Down Buck Regulator with PLL, Soft-Start and Spread Spectrum

LTC3543
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OPERATIO
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2.0 2.2 2.4 2.6 2.8 3.0
FREQUENCY (MHz)
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Figure 1b. Output Noise Spectrum of the LTC3543 Spread Spectrum
Buck Switching Converter. Note the Reduction in Fundamental and
Harmonic Peak Spectral Amplitude Compared to Figure 1a.
of a conventional buck switching converter (LTC3543
with spread spectrum operation disabled) with V_IN = 3.6V,
V_OUT = 1.5V and I_OUT = 300mA.
Unlike conventional buck converters, the LTC3543’s inter-
nal oscillator is designed to produce a clock pulse whose
frequency is randomly varied between 2MHz and 3MHz.
This has the benefit of spreading the switching noise over
a range of frequencies, significantly reducing the peak
noise. Figure 1b shows the output noise spectrum of the
LTC3543 (with spread spectrum operation enabled) with
V_IN = 3.6V, V_OUT = 1.5V and I_OUT = 300mA. Note the sig-
nificant reduction in peak output noise (≅ 20dBm).
Phase-Locked Loop Operation
A phase-locked loop (PLL) is available on the LTC3543
to synchronize the internal oscillator to an external clock
source that is connected to the MODE pin. In this case, an
external capacitor should be connected between the CAP
pin and GND to serve as part of the PLL’s loop filter. The
LTC3543’s phase detector adjusts the voltage on the CAP
pin to align the turn-on of the internal P-channel MOSFET
to the rising edge of the synchronizing signal. Note that
when the MODE pin is not being driven by an external
clock source, the MODE pin must be held to one of the
following voltage potentials: V_IN, GND, or V_FB.
The typical capture range of the LTC3543 ’s PLL is guar-
anteed over temperature to be 1MHz to 3MHz. In other
words, the LTC3543’s PLL is guaranteed to lock to an
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external clock source whose frequency is between 1MHz
and 3MHz.
Selecting the switching frequency is a tradeoff between
efficiency and component size. Low frequency opera-
tion increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
Note that the PLL is inhibited during soft-start and uses
the internal 2.25MHz frequency until regulation is estab-
lished. Also the regulator is in pulse skip mode during
PLL operation.
Short-Circuit Protection
When the output is shorted to ground, the LTC3543 senses
the high inductor current and disallows the main power
FET from turning on. The main FET is held off until the
inductor current decays to a normal level.
Dropout Operation
Depending upon the external feedback resistor ratio, it is
possible for V_IN to approach the output voltage level. As
the input supply voltage decreases to a value approaching
the output voltage, the duty cycle increases toward the
maximum on-time. Further reduction of the supply voltage
forces the main switch to remain on for more than one cycle
until it reaches 100% duty cycle. The output voltage will
then be determined by the input voltage minus the voltage
drop across the P-channel MOSFET and the inductor.
An important detail to remember is that at low input supply
voltages, the R_DS(ON) of the P-channel switch increases
(see Typical Performance Characteristics). Therefore,
the user should calculate the power dissipation when
the LTC3543 is used at 100% duty cycle with low input
voltage (See Thermal Considerations in the Applications
Information section).
Low Supply Operation
The LTC3543 will operate with input supply voltages as
low as 2.5V, but the maximum allowable output current
is reduced at this low voltage. Figure 2 shows the reduc-
tion in the maximum output current as a function of input
voltage for various output voltages.
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