LTC3543 Datasheet, PDF (11/16 Pages) Linear Technology – 600mA Synchronous Step Down Buck Regulator with PLL, Soft-Start and Spread Spectrum

LTC3543
APPLICATIO S I FOR ATIO
frequencies are the same but exhibit a phase difference,
current pulses (sourcing or sinking) are used for an amount
of time corresponding to the phase difference. The current
pulses adjust the voltage on the CAP pin until the phase
and frequency of the internal and external oscillators are
identical. At the stable operating point, the CAP pin is high
impedance and the external capacitor holds the voltage.
The external cap is used by the PLL’s loop filter to help
smooth out the voltage change and provide a stable input
to the voltage-controlled oscillator. The value of C1 will
determine how fast the loop acquires lock. Typically C1
is 1nF to 10nF in PLL mode. A value of 2.2nF is suitable
in most applications.
Using Ceramic Capacitors for C_IN, C_OUT and C1
High value, low cost ceramic capacitors are now becoming
available in smaller case sizes. Their high ripple current,
high voltage rating and low ESR make them ideal for switch-
ing regulator applications. Because the LTC3543’s control
loop does not depend on the output capacitor’s ESR for
stable operation, ceramic capacitors can be used freely to
achieve very low output ripple and small circuit size.
However, care must be taken when ceramic capacitors are
used at the input and the output. When a ceramic capacitor
is used at the input and the power is supplied by a wall
adapter through long wires, a load step at the output can
induce ringing at the input, V_IN. This ringing can couple to
the output and be mistaken as loop instability. Even worse,
the sudden inrush of current through the long wires can
potentially cause a voltage spike at V_IN, large enough to
damage the part.
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
0.6V ≤ V_OUT < 5.5V
R2
V_FB
LTC3543
R1
GND
3543 F03
Figure 3. Setting Output Voltage
Output Voltage Programming
The output voltage is set by a resistor divider according
to the following formula:
V_OUT
=
0.6V
•
⎛
⎝⎜
1+
R2 ⎞
R1⎠⎟
(4)
The external resistor divider is connected to the output
allowing remote voltage sensing as shown in Figure 3.
Efficiency Considerations
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses in LTC3543 circuits: V_IN quiescent current and
I²R losses. The V_IN quiescent current loss dominates
the efficiency loss at very low load currents whereas the
I²R loss dominates the efficiency loss at medium to high
load currents. In a typical efficiency plot, the efficiency
curve at very low load currents can be misleading since
the actual power lost is of no consequence as illustrated
in Figure 4.
500
V_OUT = 1.2V
V_OUT = 1.5V
400
V_OUT = 1.8V
V_OUT = 2.5V
300
200
100
0
0.1
1
10
100
1000
LOAD CURRENT (mA)
3543 F04
Figure 4. Power Loss vs Load Current
3543f
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