LTC3543 Datasheet, PDF (12/16 Pages) Linear Technology – 600mA Synchronous Step Down Buck Regulator with PLL, Soft-Start and Spread Spectrum

LTC3543
APPLICATIO S I FOR ATIO
1. The V_IN quiescent current is due to two components: the
DC bias current as given in the Electrical Characteristics
and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
from switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge, dQ, moves
from V_IN to ground. The resulting dQ/dt is the current out
of V_IN that is typically larger than the DC bias current. In
continuous mode, I_GATECHG = f(QT + QB) where QT and
QB are the gate charges of the internal top and bottom
switches. Both the DC bias and gate charge losses are
proportional to V_IN and thus their effects will be more
pronounced at higher supply voltages.
2. I²R losses are calculated from the resistances of the
internal switches, R_SW, and external inductor RL. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R_DS(ON) and the duty cycle
(DC) as follows:
R_SW = (R_DS(ON)TOP • DC) + (R_DS(ON)BOT • (1 – DC))
The R_DS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteristics
curves. Thus, to obtain I²R losses, simply add R_SW to
RL and multiply the result by the square of the average
output current.
Other losses, including C_IN and C_OUT ESR dissipative losses
and inductor core losses, generally account for less than
2% total additional loss.
Thermal Considerations
In most applications, the LTC3543 does not dissipate much
heat due to its high efficiency. But, in applications where the
LTC3543 is running at high ambient temperature with low
supply voltage and high duty cycles, such as in dropout,
the heat dissipated may exceed the maximum junction
temperature of the part. If the junction temperature reaches
approximately 150°C, both power switches will be turned
off and the SW node will become high impedance.
To avoid the LTC3543 from exceeding the maximum junc-
tion temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
T_R = θ_JA • P_D
where P_D is the power dissipated by the regulator and
θ_JA is the thermal resistance from the junction of the die
to the temperature.
The junction temperature, T_J, is given by:
T_J = T_A + T_R
where T_A is the ambient temperature.
As an example, consider the LTC3543 in dropout at an
input voltage of 2.7V, an ambient temperature of 80°C, and
a load current of 600mA. From the typical performance
graph of switch resistance, the R_DS(ON) of the P-channel
switch at 80°C is approximately 0.41Ω. There, power
dissipated by the part is:
P_D = I_LOAD2 • R_DS(ON) = 147.6mW
For the DFN package, the θ_JA is 64°C/W. Thus, the junction
temperature of the regulator is:
T_J = 80°C + 0.1476 • 64 = 89.4°C
which is well below the maximum junction temperature of
125°C. Note that at higher supply voltages, the junction
temperature is lower due to reduced switch resistance
(R_DS(ON)).
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V_OUT immediately shifts by an amount
equal to (ΔI_LOAD • ESR), where ESR is the effective series
resistance of C_OUT. ΔI_LOAD also begins to charge or dis-
charge C_OUT, which generates a feedback error signal.
The regulator loop then acts to return V_OUT to its steady
state value. During this recovery time, V_OUT can be moni-
tored for overshoot or ringing that would indicate a stability
3543f
12