LTC3783 Datasheet, PDF (7/24 Pages) Linear Technology – PWM LED Driver and Boost, Flyback and SEPIC Controller

LTC3783
PI FU CTIO S
FBN (Pin 1): Error Amplifier Inverting Input/Negative
Current Sense Pin. In voltage mode (V_FBP ≤ V_VREF), this
pin senses feedback voltage from either the external
resistor divider across V_OUT for output voltage regula-
tion, or the grounded sense resistor under the load for
output current regulation. In constant current/constant
voltage mode (V_FBP > 2.5V), connect this pin to the
negative side of the current-regulating resistor. Nominal
voltage for this pin in regulation is either V_FBP or (V_FBP –
100mV) for V_ILIM = 1.23V, depending on operational
mode (voltage or constant current/constant voltage) set
by the voltage at V_FBP.
FBP (Pin 2): Error Amplifier Noninverting Input/Positive
Current Sense Pin. This pin voltage determines the control
loop’s feedback mode (voltage or constant current/con-
stant voltage), the threshold of which is approximately 2V.
In voltage mode (V_FBP ≤ V_REF), this pin represents the
desired voltage which the regulated loop will cause FBN to
follow. In constant current/constant voltage mode (V_FBP >
2.5V), connect this pin to the positive side of the load
current-sensing resistor. The acceptable input ranges for
this pin are 0V to 1.23V (voltage mode) and 2.5V to 36V
(constant current/constant voltage mode).
I_LIM(Pin 3): Current Limit Pin. Sets current sense resistor
offset voltage (V_FBP – V_FBN) in constant current mode
regulation (i.e., when V_FBP > 2.5V). Offset voltage is
100mV when V_ILIM = 1.23V and decreases proportionally
with V_ILIM. Nominal voltage range for this pin is 0.1V to
1.23V.
V_REF (Pin 4): Reference Voltage Pin. Provides a buffered
version of the internal bandgap voltage, which can be
connected to FBP either directly or with attenuation.
Nominal voltage for this pin is 1.23V. This pin should never
be bypassed by a capacitor to GND. Instead, a 10k resistor
to GND should be used to lower pin impedance in noisy
systems.
FREQ (Pin 5): A resistor from the FREQ pin to ground
programs the operating frequency of the chip. The nomi-
nal voltage at the FREQ pin is 0.615V.
SYNC (Pin 6): This input allows for synchronizing the
operating frequency to an external clock and has an
internal 100k pull-down resistor.
PWMIN (Pin 7): PWM Gate Driver Input. Internal 100k
pull-up resistor. While PWMIN is low, PWMOUT is low,
GATE stops switching and the external I_TH network is
disconnected, saving the I_TH state.
PWMOUT (Pin 8): PWM Gate Driver Output. Used for
constant current dimming (LED load) or for output discon-
nect (step-up power supply).
GATE (Pin 9): Main Gate Driver Output for the Boost
Converter.
INTV_CC (Pin 10): Internal 7V Regulator Output. The main
and PWM gate drivers and control circuits are powered
from this voltage. Decouple this pin locally to the IC
ground with a minimum of 4.7µF low ESR ceramic
capacitor.
V_IN (Pin 11): Main Supply Pin. Must be closely decoupled
to ground.
SENSE (Pin 12): Current Sense Input for the Control
Loop. Connect this pin to the drain of the main power
MOSFET for V_DS sensing and highest efficiency for V_SENSE
≤ 36V. Alternatively, the SENSE pin may be connected to
a resistor in the source of the main power MOSFET.
Internal leading-edge blanking is provided for both sens-
ing methods.
SS (Pin 13): Soft-Start Pin. Provides a 50µA pull-up
current, enabled and reset by RUN, which charges an
optional external capacitor. This voltage ramp translates
into a corresponding current limit ramp through the main
MOSFET.
OV/FB (Pin 14): Overvoltage Pin/Voltage Feedback Pin. In
voltage mode (V_FBP ≤ V_REF), this input, connected to V_OUT
through a resistor network, sets the output voltage at
which GATE switching is disabled in order to prevent an
overvoltage situation. Nominal threshold voltage for the
OV pin is 1.32V (V_REF + 7%) with 20mV hysteresis. In
current/voltage mode (V_FBP > 2.5V), this pin senses V_OUT
through a resistor divider and brings the loop into voltage
regulation such that pin voltage approaches V_REF = 1.23V,
provided the loop is not regulating the load current (e.g.,
[V_FBP – V_FBN] < 100mV for I_LIM = 1.23V).
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