LTC3330_15 Datasheet, PDF (5/32 Pages) Linear Technology – Nanopower Buck-Boost DC/DC with Energy Harvesting Battery Life Extender

LTC3330
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at T_A = 25°C (Note 2). V_IN = 5V, BAT = 3.6V, SCAP = OV, LDO_IN = 0V unless
otherwise specified.
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
R_{N_BB}
Buck-Boost NMOS Input and Output Switch
On-Resistance
IPK2 = 1
IPK2 = 0
0.6
Ω
3.8
Ω
I_LEAK(P)
I_LEAK(N)
PMOS Switch Leakage
NMOS Switch Leakage
Maximum Buck Duty Cycle
Buck/Buck-Boost Regulators
Buck/Buck-Boost Regulators
Buck/Buck-Boost Regulators
–20
–20
l 100
20
nA
20
nA
%
V_{LDO_IN}
I_{LDO_IN}
I_{LDO_OUT}
LDO_OUT
LDO_IN Input Range
LDO_IN Quiescent Current
LDO_OUT Leakage Current
Regulated LDO Output Voltage
l 1.8V
5.5V
V
LDO_IN = 5.0V, I_{LDO_OUT} = 0mA
LDO_OUT = 3.3V, LDO[2:0] = 110
400
600
nA
100
150
nA
Error as a Percentage of Target, 100µA
Load
–2.0
l –3.0
2.0
%
3.0
%
LDO Line Regulation (1.8V to 5.5V)
LDO_OUT = 1.2V, 10mA Load
2
mV/V
LDO Load Regulation (10µA to 10mA)
LDO_IN = 5.0V, LDO_OUT = 3.3V
0.5
mV/mA
LDO Dropout Voltage
LDO_OUT = 3.3V, 10mA LOAD
50
mV
R_{P_LDO} LDO PMOS Switch On-Resistance
LDO_IN = 3.3V, I_{LDO_OUT} = 10mA
5
Ω
LDO Current Limit
LDO_IN = 5.0V
50
mA
PGLDO Rising Threshold
As a Percentage of the 3.3V LDO_OUT
l 88
92
96
%
Target
PGLDO Falling Threshold
As a Percentage of the 3.3V LDO_OUT
l 86
90
94
%
Target
V_SCAP
I_SCAP
I_SOURCE
I_SINK
V_BAL
V_IH
Supercapacitor Balancer Input Range
Supercapacitor Balancer Quiescent Current
Supercapacitor Balancer Source Current
Supercapacitor Balancer Sink Current
Supercapacitor Balance Point
Digital Input High Voltage
SCAP = 5.0V
SCAP = 5.0V, BAL = 2.4V
SCAP = 5.0V, BAL = 2.6V
Percentage of SCAP Voltage
Pins LDO_EN, OUT[2:0], LDO[2:0],
IPK[2:0], UV[3:0]
l 2.5
5.5
V
150
225
nA
10
mA
10
mA
l 49
50
51
%
l 1.2
V
V_IL
Digital Input Low Voltage
Pins LDO_EN, OUT[2:0], LDO[2:0],
l
IPK[2:0], UV[3:0]
0.4
V
I_IH
Digital Input High Current
Pins LDO_EN, OUT[2:0], LDO[2:0],
IPK[2:0], UV[3:0]
0
10
nA
I_IL
Digital Input Low Current
Pins LDO_EN, OUT[2:0], LDO[2:0],
IPK[2:0], UV[3:0]
0
10
nA
V_OH
PGVOUT, PGLDO Output High Voltage
EH_ON Output High Voltage
BAT = 5V, 1µA Out of Pin
V_IN = 6V, 1µA Out of Pin
V_OL
PGVOUT, PGLDO, EH_ON Output Low Voltage BAT = 5V, 1µA into Pin
l 4.0
l 3.8
l
V
V
0.4
V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3330E is tested under pulsed load conditions such that
T_J ≈ T_A. The LTC3330E is guaranteed to meet specifications from 0°C to
85°C. The LTC3330I is guaranteed over the –40°C to 125°C operating
junction temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors.
Note 3: T_J is calculated from the ambient T_A and power dissipation PD
according to the following formula: T_J = T_A + (P_D • θ_JA).
Note 4: Dynamic supply current is higher due to gate charge being
delivered at the switching frequency.
Note 5: The PGVOUT Rising threshold is equal to the sleep threshold. See
V_OUT specification.
For more information www.linear.com/LTC3330
3330fb
5