LTC3330_15 Datasheet, PDF (24/32 Pages) Linear Technology – Nanopower Buck-Boost DC/DC with Energy Harvesting Battery Life Extender

LTC3330
APPLICATIONS
Summary of Digital Inputs and Outputs
There are 14 digital pin-strapped logic inputs to the
LTC3330 and three digital logic outputs. These and the
rails they are referenced to are summarized in Table 8.
Table 8. Digital Pin Summary
INPUT PIN
UV[3:0]
IPK[2:0]
OUT[2:0]
LDO[2:0]
LDO_EN
LOGIC HIGH LEVEL
V_IN2
V_IN3
V_IN3
LDO_IN
LDO_IN up to 6V
LTC3330 System Solutions
The LTC3330 can be paired with other Linear Technology low
quiescent current integrated circuits to form a multirail sys-
tem. Figure 7 shows an LTC3330 powering an LTC3388-3
from its 5V output. The LTC3388-3, an 800nA Buck
converter, is configured here to produce a negative 5V
rail by tying the V_OUT pin to ground and tying its GND pin
to the regulated –5V output. The result is a ±5V energy
harvesting power supply with battery backup.
OUTPUT PIN
PGVOUT
PGLDO
EH_ON
LOGIC HIGH LEVEL
MAX (BAT, V_IN2, V_OUT)
MAX (BAT, V_IN2, V_OUT)
V_IN3
MIDE V25W
22µF
1µF, 6.3V
25V
4.7µF, 6.3V
AC2
V_IN
CAP
V_IN2
LTC3330
AC1
SW
V_OUT
SCAP
UV3
BAL
UV2
UVLOR = 12V**
UVLOF = 11V
UV1
IPEAK_BB = 250mA
UV0
LDO_IN
LDO2
LDO1
+
Li-ION
22µH
4.7µF
6.3V
LDO0
BAT
LDO_EN
SWA
PGVOUT
PG_LDO
SWB
EH_ON
LDO_OUT
GND
V_IN3
IPK2 IPK1 IPK0 OUT2 OUT1 OUT0
22µH
5V
22µF
6.3V
V_IN
1µF, 6.3V
PGOOD
LTC3388-3*
CAP
2.2µF
10V
V_IN2
22µH
SW
4.7µF
EN
V_OUT
6.3V
D1
22µF
6.3V
D0
STBY
GND
3.3V
1µF
22µF
6.3V
6.3V
*EXPOSED PAD MUST BE ELECTRICALLY ISOLATED FROM
SYSTEM GROUND AND CONNECTED TO THE –5V RAIL
–5V
3330 F07
**FOR PEAK POWER TRANSFER, CENTER THE UVLO WINDOW
AT HALF THE RECTIFIED OPEN CIRCUIT VOLTAGE OF THE PIEZO
Figure 7. Dual ±5V Power Supply with a 3.3V LDO Output
3330fb
24
For more information www.linear.com/LTC3330