LTC3577-3 Datasheet, PDF (39/52 Pages) Linear Technology – Highly Integrated Portable Product PMIC

LTC3577-3/LTC3577-4
OPERATION
When the LTC3577-3/LTC3577-4 are read from, they re-
lease the SDA line so that the master may acknowledge
receipt of the data. Since the LTC3577-3/LTC3577-4 only
transmit one byte of data, a master not acknowledging the
data sent by the LTC3577-3/LTC3577-4 has no I²C specific
consequence on the operation of the I²C port.
I²C Slave Address
The LTC3577-3/LTC3577-4 respond to a 7-bit address
which has been factory programmed to b’0001001[R/W]’.
The LSB of the address byte, known as the read/write bit,
should be 0 when writing data to the LTC3577-3/LTC3577-4
and 1 when reading data from it. Considering the address
an eight bit word, then the write address is 0x12 and the
read address is 0x13. The LTC3577-3/LTC3577-4 will
acknowledge both its read and write address.
I²C Sub-Addressed Writing
The LTC3577-3/LTC3577-4 have four command registers
for control input. They are accessed by the I²C port via a sub-
addressed writing system.
Each write cycle of the LTC3577-3/LTC3577-4 consists of
exactly three bytes. The first byte is always the LTC3577-3/
LTC3577-4’s write address. The second byte represents the
LTC3577-3/LTC3577-4’s sub-address. The sub address is a
pointer which directs the subsequent data byte within the
LTC3577-3/LTC3577-4. The third byte consists of the data
to be written to the location pointed to by the sub-address.
The LTC3577-3/LTC3577-4 contain control registers at only
four sub-address locations: 0x00, 0x01, 0x02 and 0x03.
Writing to sub-addresses outside the four sub-addresses
listed is not recommended as it can cause data in one of
the four listed sub-addresses to be overwritten.
I²C Bus Write Operation
The master initiates communication with the LTC3577-3/
LTC3577-4 with a START condition and the LTC3577-3/
LTC3577-4’s write address. If the address matches that
of the LTC3577-3/LTC3577-4, the LTC3577-3/LTC3577-4
return an acknowledge. The master should then deliver
the sub-address. Again the LTC3577-3/LTC3577-4 ac-
knowledge and the cycle is repeated for the data byte.
The data byte is transferred to an internal holding latch
upon the return of its acknowledge by the LTC3577-3/
LTC3577-4. This procedure must be repeated for each
sub-address that requires new data. After one or more
cycles of [ADDRESS][SUB-ADDRESS][DATA], the master
may terminate the communication with a STOP condition.
Alternatively, a REPEAT-START condition can be initiated
by the master and another chip on the I²C bus can be
addressed. This cycle can continue indefinitely and the
LTC3577-3/LTC3577-4 will remember the last input of valid
data that it received. Once all chips on the bus have been
addressed and sent valid data, a global STOP can be sent
and the LTC3577-3/LTC3577-4 will update their command
latches with the data that they had received.
I²C Bus Read Operation
The bus master reads the status of the LTC3577-3/
LTC3577-4 with a START condition followed by the
LTC3577-3/LTC3577-4 read address. If the read address
matches that of the LTC3577-3/LTC3577-4, the LTC3577-3/
LTC3577-4 return an acknowledge. Following the acknowl-
edgement of their read address, the LTC3577-3/LTC3577-4
return one bit of status information for each of the next
8 clock cycles. A STOP command is not required for the
bus read operation.
I²C Input Data
There are 4 bytes of data that can be written to on the
LTC3577-3/LTC3577-4. The bytes are accessed through
the sub-addresses 0x00 to 0x03. At first power applica-
tion (V_BUS, WALL or BAT) all bits default to 0. Addition-
ally all bits are cleared to 0 when DV_CC drops below its
undervoltage lock out or if the pushbutton enters the
power down (PDN) state.
Table 8 shows the first byte of data that can be written to
at sub-address 0x00. This byte of data is referred to as
the “buck control register”.
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