LTC3577-3 Datasheet, PDF (28/52 Pages) Linear Technology – Highly Integrated Portable Product PMIC

LTC3577-3/LTC3577-4
OPERATION
Overvoltage Protection (OVP)
The LTC3577-3/LTC3577-4 can protect themselves from
the inadvertent application of excessive voltage to V_BUS or
WALL with just two external components: an N-channel
FET and a 6.2k resistor. The maximum safe overvoltage
magnitude will be determined by the choice of the external
NMOS and its associated drain breakdown voltage.
The overvoltage protection module consists of two pins.
The first, OVSENS, is used to measure the externally applied
voltage through an external resistor. The second, OVGATE,
is an output used to drive the gate pin of an external FET.
The voltage at OVSENS will be lower than the OVP input
voltage by (I_OVSENS • 6.2kΩ) due to the OVP circuit’s
quiescent current. The OVP input will be 200mV to 400mV
higher than OVSENS under normal operating conditions.
When OVSENS is below 6V, an internal charge pump will
drive OVGATE to approximately 1.88 • OVSENS. This will
enhance the N-channel FET and provide a low impedance
connection to V_BUS or WALL which will, in turn, power
the LTC3577-3/LTC3577-4. If OVSENS should rise above
6V (6.35V OVP input) due to a fault or use of an incorrect
wall adapter, OVGATE will be pulled to GND, disabling the
external FET to protect downstream circuitry. When the
voltage drops below 6V again, the external FET will be
re-enabled.
In an overvoltage condition, the OVSENS pin will be
clamped at 6V. The external 6.2k resistor must be
sized appropriately to dissipate the resultant power.
For example, a 1/10W 6.2k resistor can have at most
√P_MAX • 6.2k = 24V applied across its terminals. With the
6V at OVSENS, the maximum overvoltage magnitude that
this resistor can withstand is 30V. A 1/4W 6.2k resistor
raises this value to 45V.
The charge pump output on OVGATE has limited output
drive capability. Care must be taken to avoid leakage on
this pin, as it may adversely affect operation.
Dual Input Overvoltage Protection
It is possible to protect both V_BUS and WALL from
overvoltage damage with several additional components,
as shown in Figure 5. Schottky diodes D1 and D2 pass the
larger of V1 and V2 to R1 and OVSENS. If either V1 or V2
exceeds 6V plus V_F(SCHOTTKY), OVGATE will be pulled to
GND and both the WALL and USB inputs will be protected.
Each input is protected up to the drain-source breakdown,
BVDSS, of MN1 and MN2. R1 must also be rated for the
power dissipated during maximum overvoltage. See the
“Overvoltage Protection” section for an explanation of this
calculation. Table 2 shows some NMOS FETs that maybe
suitable for overvoltage protection.
Table 2. Recommended Overvoltage FETs
NMOS FET
Si1472DH
BVDSS
30V
R_ON
82mΩ
Si2302ADS
20V
60mΩ
Si2306BDS
30V
65mΩ
Si2316BDS
30V
80mΩ
IRLML2502
20V
35mΩ
PACKAGE
SC70-6
SOT-23
SOT-23
SOT-23
SOT-23
MN1
V1
WALL
LTC3577-3/
LTC3577-4
OVGATE
V2
V_BUS
D2
D1 ^MN2
C1
R1
OVSENS
357734 F05
Figure 5. Dual Input Overvoltage Protection
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357734fa