LTC3577-3 Datasheet, PDF (29/52 Pages) Linear Technology – Highly Integrated Portable Product PMIC

LTC3577-3/LTC3577-4
OPERATION
Reverse Input Voltage Protection
The LTC3577-3/LTC3577-4 can also be easily protected
against the application of reverse voltage as shown in
Figure 6. D1 and R1 are necessary to limit the maximum
VGS seen by MP1 during positive overvoltage events. D1’s
breakdown voltage must be safely below MP1’s BVGS. The
circuit shown in Figure 6 offers forward voltage protection
up to MN1’s BVDSS and reverse voltage protection up to
MP1’s BVDSS.
USB/WALL
ADAPTER
MP1
MN1
D1
R1
R2
500k
6.2k
V_BUS
C1 _LTC3577-3/
LTC3577-4
OVGATE
OVSENS
D1: 5.6V ZENER
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MP1: Si2323 DS, BVDSS = 20V
V_BUS POSITIVE PROTECTION UP TO BVDSS OF MN1
V_BUS NEGATIVE PROTECTION UP TO BVDSS OF MP1
Figure 6. Dual Polarity Voltage Protection
LOW DROPOUT LINEAR REGULATOR OPERATION
LDO Operation and Voltage Programming
The LTC3577-3/LTC3577-4 contain two 150mA adjustable
output LDO regulators. The first LDO (LDO1) is always on
and will be enabled whenever V_OUT is greater than V_OUT
UVLO. The second LDO (LDO2) is controlled by the push-
button and is the first supply to sequence up in response
to pushbutton application. Both LDOs are disabled when
V_OUT is less than V_OUT UVLO and LDO2 is further disabled
when the pushbutton circuity is in the power down or
power off states. Both LDOs contain a soft-start function
to limit inrush current when enabled. The soft-start func-
tion works by ramping up the LDO reference over a 200μs
period (typical) when the LDO is enabled.
When disabled all LDO circuitry is powered off leaving
only a few nanoamps of leakage current on the LDO sup-
ply. Both LDO outputs are individually pulled to ground
through internal resistors when disabled.
The power good status bits of LDO1 and LDO2 are avail-
able in I²C through the read-back registers PGLDO[1] and
PGLDO[2] for LDO1 and LDO2 respectively. The power
good comparators for both LDOs are sampled when the
I²C port receives the correct I²C read address.
Figure 7 shows the LDO application circuit. The full-scale
output voltage for each LDO is programmed using a resistor
divider from the LDO output (LDO1 or LDO2) connected
to the feedback pins (LDO1_FB or LDO2_FB) such that:
V_LDOx
=
0.8V
•
⎛
⎝⎜
R1
R2
+
1^{⎞⎠⎟}
For stability, each LDO output must be bypassed to ground
with a minimum 1μF ceramic capacitor (C_OUT).
LDOxEN ⁰
1
V_INLDOx
MP
LDOx
R1
LDOx_FB
0.8V
GND
R2
LDOx
OUTPUT
C_OUT
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Figure 7. LDO Application Circuit
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