LT3752_15 Datasheet, PDF (35/52 Pages) Linear Technology – Active Clamp Synchronous Forward Controllers with Internal Housekeeping Controller

LT3752/LT3752-1
APPLICATIONS INFORMATION
Programming Active Clamp Switch Timing: AOUT to
OUT (t_AO) and OUT to AOUT (t_OA) Delays
The timings t_AO and t_OA represent the delays between AOUT
and OUT edges (Figures 1 and 2) and are programmed
by a single resistor, R_TAO, connected from analog ground
(Pin 18) to the T_AO pin. Once t_AO is programmed for the
reasons given below, t_OA will be automatically generated.
Front-end timing t_AO (M2 off, M1 on)
= AOUT(edge)-to-OUT(rising)
=
50ns
+
3.8ns
•


R_TAO
1k ^
,
14.7k
<
R_TAO
<
125k
In order to minimize turn-on transition loss in M1 the drain
of M1 should be as low as possible before M1 turns on.
To achieve this, AOUT should turn M2 off a delay of t_AO
before OUT turns M1 on. This allows the main transformer’s
magnetizing current to discharge M1 drain voltage quickly
towards V_IN before M1 turns on.
As SWP falls below V_IN, however, the rectifying diodes on
the secondary side are typically active and clamp the SWP
node close to V_IN. If enough leakage inductance exists,
however, the clamping action on SWP by the secondary
side will be delayed—potentially allowing the drain of
M1 to be fully discharged to ground just before M1 turns
on. Even with this delay due to the leakage inductance,
L_MAG needs to be low enough to allow I_MAG to be negative
enough to slew SWP down to ground before M1 turns on.
If achievable, M1 will experience zero voltage switching
(ZVS) for highest efficiency. As will be seen in a later sec-
tion entitled Primary-Side Power MOSFET Selection, M1
transition loss is a significant contributor to M1 losses.
Back-end timing t_OA (M1 off, M2 on) is automatically
generated
= OUT(falling)-to-AOUT(edge) = 0.9 • t_AO
t_OA should be checked to ensure M2 is not turned on until
M1 and M3 are turned off.
Programming Synchronous Rectifier Timing: SOUT to
OUT (t_SO) and OUT to SOUT (t_OS) Delays
The LT3752/LT3752-1 include a ±0.4A gate driver at the
SOUT pin to send a control signal via a pulse transformer
to the secondary side of the forward converter for syn-
chronous rectification (see Figures 1 and 2). For the
highest efficiency, M4 should be turned on whenever M1
is turned off. This suggests that SOUT should be a non-
overlapping signal with OUT with very small non-overlap
times. Inherent timing delays, however, which can vary
from application to application, can exist between OUT to
CSW and between SOUT to CG. Possible shoot-through
can occur if both M1 and M4 are on at the same time,
resulting in transformer and/or switch damage.
Front-end timing: t_SO (M4 off, M1 on)
= SOUT(falling)-to-OUT(rising) delay
= t_SO = t_AO – t_AS
= 3.8ns • (R_TAS – R_TAO)
where:
t_AS = 50ns + (3.8ns • R_TAS/1k) , 14.7k < R_TAS < 125k,
t_AO = 50ns + (3.8ns • R_TAO/1k), 14.7k < R_TAO < 125k,
t_SO is defined by resistors R_TAS and R_TAO connected from
analog ground (Pin 18) to their respective pins T_AS and
T_AO. Each of these resistor defines a delay referenced
to the AOUT edge at the start of each cycle. R_TAO was
already programmed based on requirements defined in
the previous section Programming AOUT to OUT Delay.
R_TAS is then programmed as a delay from AOUT to SOUT
to fulfill the equation above for t_SO. By choosing R_TAS less
than or greater than R_TAO, the delay between SOUT falling
and OUT rising can be programmed as positive or nega-
tive. While a positive delay can always be programmed
for t_SO, the ability to program a negative delay allows for
improved efficiency if OUT(rising)-to-CSW(rising) delay
is larger than SOUT(falling)-to-CG(rising) delay.
For more information www.linear.com/LT3752
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