LT3752_15 Datasheet, PDF (29/52 Pages) Linear Technology – Active Clamp Synchronous Forward Controllers with Internal Housekeeping Controller

LT3752/LT3752-1
APPLICATIONS INFORMATION
stops immediately and the SS1/SS2 pins are rapidly
discharged. The absence of switching reduces the sense
voltage at the OC pin, allowing SS1/SS2 pins to recharge
and eventually attempt switching again. The part exists
in this hiccup mode as long as the overcurrent condition
exists. This protects the converter and reduces power
dissipation in the components (see Hard Stop in the
Applications Information section). The 96mV peak switch
current threshold is independent of the voltage drop in
R_ISLP used for slope compensation.
Output DC load current to trigger hiccup mode:
LOAD(OVERCURRENT)
( ) ⁼
N_P
^NS
•
96mV
R_ISENSE


–
1/2 I_RIPPLE(P-P)
where:
N_P = forward transformer primary turns
N_S = forward transformer secondary turns
I_RIPPLE(P-P) = Output inductor peak-to-peak ripple
current
R_ISENSE should be programmed to allow maximum DC load
current for the application plus enough margin during load
transients to avoid overcurrent hiccup mode.
Programming Maximum Duty Cycle Clamp: D_VSEC
(Volt-Second Clamp)
Unlike other converters which only provide a fixed maxi-
mum duty cycle clamp, the LT3752/LT3752-1 provide an
accurate programmable maximum duty cycle clamp
(D_VSEC) on the OUT pin which moves inversely with
system input. D_VSEC provides a duty cycle guardrail to
limit the volt-seconds-on product over the entire natural
duty cycle range (Figures 11 and 12). This limits the
drain voltage required for complete transformer reset.
t_{ON_VSEC}
OUT
t_ON
D = t_ON/t
t
(PROGRAMMED
BY R_IVSEC)
DV_SEC = t_{ON_VSEC}/t
DV_SEC = “DUTY CYCLE GUARDRAIL”
3752 F11
Figure 11. Volt-Second (D_VSEC) Clamp
SYSTEM
INPUT
R1
R2 _TO
OVLO
R3 ^PIN
UVLO_V_SEC
LT3752/LT3752-1
IVSEC
RT
R_IVSEC
R_T
3752 F12
Figure 12. Programming D_VSEC
A resistor R_IVSEC from the IVSEC pin to analog ground
(Pin 18) programs D_VSEC.
D_VSEC (OUT pin duty cycle clamp)
= 0.725 • ^RIVSEC • ^fOSC • ^1.25
51.1k 300 UVLO_V_SEC
where:
R_IVSEC = programming resistor at IVSEC pin
f_OSC = switching frequency (kHz)
UVLO_V_SEC = resistor divided system input voltage
R_IVSEC can program any D_VSEC required at minimum
system input. D_VSEC will then follow natural duty cycle
as V_IN varies. Maximum programmable D_VSEC is typi-
For more information www.linear.com/LT3752
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