LTM4676A_15 Datasheet, PDF (34/130 Pages) Linear Technology – Dual 13A or Single 26A Module Regulator with Digital Power System Management

LTM4676A
Operation
The degradation in EEPROM retention for temperatures
>125°C can be approximated by calculating the dimen-
sionless acceleration factor using the following equation:
AF
=
⎡⎛
e^{⎣⎢⎝⎜}
Ea
k
⎞⎠⎟_•^{⎛⎝⎜}
1
TUSE +273
–
1
TSTRESS +273
⎞⎤
⎟⎥
⎠⎦
set in the STATUS_BYTE and STATUS_WORD commands,
the appropriate bit is set in the STATUS_MFR_SPECIFIC
command, and the ALERT pin will be pulled low. EEPROM
repair can be attempted by writing the desired configuration
to the controller and executing a STORE_USER_ALL
command followed by a CLEAR_FAULTS command.
where:
AF = acceleration factor
Ea = activation energy = 1.4eV
K = 8.617 • 10^–5 eV/°K
T_USE = 125°C specified junction temperature
T_STRESS = actual junction temperature in °C
Example: Calculate the effect on retention when operating
at a junction temperature of 135°C for 10 hours.
The LTM4676A manufacturing section of the EEPROM
is mirrored. The LTM4676A has the ability to operate if
either one of the two sections of the manufacturing sec-
tion of the EEPROM configuration becomes corrupted.
If a discrepancy is detected, the “NVM CRC Fault” in the
STATUS_MFR_SPECIFIC command is set. If this bit
remains set after being cleared by issuing a CLEAR_FAULTS
or writing a 1 to this bit, an irrecoverable internal fault has
occurred. There are no provisions for field repairing un-
recoverable EEPROM faults in the manufacturing section.
T_STRESS = 130°C
T_USE = 125°C
AF= e^{[(1.4/8.617 • 10–5) • (1/398 – 1/403)]} = 1.66
The equivalent operating time at 125°C = 16.6 hours.
Thus the overall retention of the EEPROM was degraded
by 6.6 hours as a result of operating at a junction tempera-
ture of 130°C for 10 hours. The effect of the overstress
is negligible when compared to the overall EEPROM
retention rating of 87,600 hours at a maximum junction
temperature of 125°C.
The integrity of the EEPROM is checked with a CRC
calculation each time its data is read, such as after a
power-on reset or execution of a RESTORE_USER_ALL or
MFR_RESET command. If CRC error occurs, the MFR bit is
set in the STATUS_BYTE and STATUS_WORD commands.
The NVM CRC error bit in the STATUS_MFR_SPECIFIC
command is set and the ALERT and RUN pins are pulled
low disabling the output as a safety measure. The device
will only respond at special address 0x7C or global ad-
dresses 0x5A and 0x5B.
Serial Interface
The LTM4676A serial interface is a PMBus compliant slave
device and can operate at any frequency between 10kHz
and 400kHz. The address is configurable using either
the EEPROM or an external resistor divider. In addition
the LTM4676A always responds to the global broadcast
address of 0x5A (7 bit) or 0x5B (7 bit). Address 0x5A
is not paged and is performed on both channels. 0x5B
respects the page command. Because address 0x5A
does not support page, it can not be used for any paged
reading commands.
The serial interface supports the following protocols
defined in the PMBus specifications: 1) send command,
2) write byte, 3) write word, 4) group, 5) read byte, 6)
read word and 7) read block 8) PAGE_PLUS_READ,
9) PAGE_PLUS_WRITE 10) SMBALERT_MASK read,
11) SMBALERT_MASK write. All read operations will
return a valid PEC if the PMBus master requests it. If the
PEC_REQUIRED bit is set in the MFR_CONFIG_ALL com-
mand, the PMBus write operations will not be acted upon
until a valid PEC has been received by the LTM4676A.
CRC Protection
The integrity of the EEPROM memory is checked after a
power-on reset. A CRC error will prevent the controller from
leaving the OFF state. If a CRC error occurs, the CML bit is
Communication Protection
PEC write errors (if PEC_REQUIRED is active), attempts
to access unsupported commands, or writing invalid data
to supported commands will result in a CML fault. The
4676af
34
For more information www.linear.com/LTM4676A