LTM4676A_15 Datasheet, PDF (16/130 Pages) Linear Technology – Dual 13A or Single 26A Module Regulator with Digital Power System Management

LTM4676A
Pin Functions
V_OUT0CFG, V_TRIM0CFG and the Applications Information
section.) Minimize capacitance—especially when the pin
is left open—to assure accurate detection of the pin state.
Note that use of RCONFIGs on V_OUT1CFG/V_TRIM1CFG can
affect the V_OUT1 range setting (MFR_PWM_MODE₁[1])
and loop gain.
V_TRIM1CFG (H6): Output Voltage Select Pin for V_OUT1, Fine
Setting. Works in combination with V_OUT1CFG to affect
the VOUT_COMMAND (and associated output voltage
monitoring and protection/fault-detection thresholds)
of Channel 1, at SV_IN power-up. (See V_OUT1CFG and the
Applications Information section.) Minimize capacitance—
especially when the pin is left open—to assure accurate
detection of the pin state. Note that use of RCONFIGs on
V_OUT1CFG/V_TRIM1CFG can affect the V_OUT1 range setting
(MFR_PWM_MODE₁[1]) and loop gain.
SYNC (E7): PWM Clock Synchronization Input and Open-
Drain Output Pin. The setting of the FREQUENCY_SWITCH
command dictates whether the LTM4676A is a “sync
master” or “sync slave” module. When the LTM4676A
is a sync master, FREQUENCY_SWITCH contains the
commanded switching frequency of Channels 0 and 1—in
PMBus linear data format—and it drives its SYNC pin low
for 500ns at a time, at this commanded rate. In contrast,
a sync slave uses MFR_CONFIG_ALL[4]=1_b and does not
pull its SYNC pin low. The LTM4676A’s PLL synchronizes
the LTM4676A’s PWM clock to the waveform present on
the SYNC pin—and therefore, a resistor pull-up to 3.3V
is required in the application, regardless of whether the
LTM4676A is a sync master or slave. EXCEPTION: driving
the SYNC pin with an external clock is permissible; see
the Applications Information section for details.
SCL (E6): Serial Bus Clock Open-Drain Input (Can Be an
Input and Output, if Clock Stretching is Enabled). A pull-up
resistor to 3.3V is required in the application for digital
communication to the SMBus master(s) that nominally
drive this clock. The LTM4676A will never encounter
scenarios where it would need to engage clock stretching
unless SCL communication speeds exceed 100kHz—and
even then, LTM4676A will not clock stretch unless clock
stretching is enabled by means of setting MFR_CONFIG_
ALL[1] = 1_b. The factory-default NVM configuration
setting has MFR_CONFIG_ALL[1] = 0_b: clock stretching
disabled. If communication on the bus at clock speeds
above 100kHz is required, the user’s SMBus master(s)
need to implement clock stretching support to assure
solid serial bus communications, and only then should
MFR_CONFIG_ALL[1] be set to 1_b. When clock stretch-
ing is enabled, SCL becomes a bidirectional, open-drain
output pin on LTM4676A.
SDA (D6): Serial Bus Data Open-Drain Input and Output.
A pull-up resistor to 3.3V is required in the application.
ALERT (E5): Open-Drain Digital Output. A pull-up resistor
to 3.3V is required in the application only if SMBALERT
interrupt detection is implemented in one’s SMBus system.
SHARE_CLK (H7): Share Clock, Bidirectional Open-
Drain Clock Sharing Pin. Nominally 100kHz. Used for
synchronizing the time base between multiple LTM4676As
(and any other Linear Technology devices with a SHARE_
CLK pin)—to realize well-defined rail sequencing and rail
tracking. Tie the SHARE_CLK pins of all such devices
together; all devices with a SHARE_CLK pin will synchronize
to the fastest clock. A pull-up resistor to 3.3V is only re-
quired when synchronizing the time base between devices.
GPIO₀, GPIO₁ (E4 and F4, Respectively): Digital,
Programmable General Purpose Inputs and Outputs.
Open-drain outputs and/or high impedance inputs. The
LTM4676A’s factory-default NVM configurations for
MFR_GPIO_PROPAGATE_n—0x6893—and MFR_GPIO_
RESPONSE_n—0xC0—are such that: (1) when a channel-
specific fault condition is detected—such as channel OT
(overtemperature) or output UV/OV—the respective GPIO_n
pin pulls logic low; (2) when a non-channel specific fault
condition is detected—such as input OV or control IC
OT—both GPIO_n pins pull logic low; (3) the LTM4676A
ceases switching action on Channel 0 and 1 when its
respective GPIO_n pin is logic low. Most significantly, this
default configuration provides for graceful integration and
inter-operation of LTM4676A with paralleled channel(s) of
other LTM4676A(s)—in terms of properly coordinating
efforts in starting, ceasing, and resuming switching
action and output voltage regulation, in unison—all
without GUI intervention or the need to “custom-
preprogram” module NVM contents. Pull-up resistors
from GPIO_n to 3.3V are required for proper operation in
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